SU1411831A1 - Digital delay line - Google Patents

Abstract

The invention relates to computing and can be used as a controlled digital hold line. The purpose of the invention is to enhance the functionality of the digital delay line by changing its information capacity. Set goal wasp. This is due to the fact that the write occurs by a number equal to the sum of the codes from the output of counter 1 and the input control code N, and the reading is set to the code set at the output of the counter through N clock pulses. The device comprises a counter 1, an adder 2, a driver of 3 pulses, a multiplexer 4, a block 5 of memory. 2 Il.

Description

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The invention relates to computing technology and can be used as a controllable digital delay line. ; The purpose of the invention is to enhance the functionality of a digital esuction line by changing its information capacity.

FIG. 1 shows a functional circuit of a controlled digital delay line; in fig. 2 - timing charts of the clock pulse generator.

The digital delay line contains a counter 1, an adder 2 (there is two mod modules), a shaper 3 clocks, a multiplexer 4, a block 5 of memory.

Digital delay line works as follows.

With the arrival of the clock pulse (Fig. 2a) at the input of the imaging unit 3, the signals shown in Fig. 2 are formed at its outputs. 26 and c. The signal from the first output of the imaging unit 3 (Fig. 2c) reads information from block 5 at the address set at the output of the counter 1. With | a negative pulse | at the second output of the imaging unit 3: (Fig. 26), The information from the output of block 5, block 5 goes | to the recording mode, and at its address input the code from the output of adder 2 is set equal to the sum of the input (control code N and the code from the output of the counter. 1. With the appearance of the second: a negative pulse at the first output of the imaging unit 3 (Fig. 2c) is recording the information set on the information input of the unit 5, the address set to the address bus address.With a positive difference from the second output of the imaging unit 3, the content of the counter 1 is increased by; unit.

Due to the fact that the recording of information occurs on a number equal to the sum of the code from the output of counter 1 and the input control code N, and the reading on the code set to

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the output of counter 1, through the N clock pulses, the input information on the recorder.

With a change in the input control code, there is a change in the information capacity of the digital delay line. The maximum information capacity of the digital delay line is determined by the capacity of block 5. The speed of the digital delay line is determined by the frequency of the clock, which, in turn, is determined by the speed of block 5.

Formula of invention

A digital delay line containing a memory unit, a multiplexer, a counter, the outputs of which are connected to the first group of information multiplexer inputs, the information inputs of the memory block are respectively the information inputs of a digital delay line, characterized in that, in order to extend the functionality of the line delays due to a change in its information capacity, a modulo two modulator, a clock generator, whose input is a clock input of a digital line for the first output of which is connected to the control input of the memory block, the control input of the multiplexer and the counting input of the counter, the second output of the pulse shaper is connected to the control input of the memory, whose outputs are the information outputs of the digital delay line, the multiplexer outputs are connected respectively to the group of address inputs of the memory block, the first group of inputs of the adder is connected respectively to the group of outputs of the counter, and the second group of inputs is sum-. The torus is the input of the control code setting of the digital delay line, the outputs of the adder are connected to the second group of information inputs of the 1 × 1 hex signals.

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Claims (1)

Claim A digital delay line containing a memory unit, a multiplexer, a counter whose outputs are connected respectively to the first group of information inputs of the multiplexer, the information inputs of the memory unit are respectively the information inputs of a digital delay line, characterized in that, in order to expand the functionality of the delay line due to changes in its information capacity, an adder modulo two is introduced into it, a clock shaper, the input of which is the clock input of the digital line ratio, first. the output of which is connected to the control input of the memory block record, the control input of the multiplexer and the counting input of the counter, the second output of the pulse shaper is connected to the control input by reading the memory block, the outputs of which are respectively the information outputs of the digital delay line, the outputs of the multiplexer are connected respectively to the group of address inputs of the memory block , the first group of inputs of the adder is connected respectively to the group of outputs of the counter, and the second group of inputs of the adder is the inputs of SETTING digital delay line control codes, the adder outputs are connected to the second group of information inputs of the multiplexer. P II I__________________I________________ ^ff ----- 1 Г ------ 1 I ------ 1 1 ------ L_r ^e_ 4JTJ ~ njT_r ^__ LrLJ — Ί_Π_Γ ¢ 1 / 2.2