SU1755367A1 - Device for generating pulse trains - Google Patents

Abstract

The essence of the invention: the device contains: 1 reference pulse generator 1, 5 counting blocks 2, 3, 4, 5 and 17, 4 flip-flops 6, 7, 9 and 10, 1 inverter 8, 6 elements OR NOT 11, 12, 13, 14, 15 and 16, 4 programmable memory blocks 18, 19, 20 and 21, 1 decoder 22, element OR 23 and 24, 1 delay element 25, 1 control bus 26, 1 output bus 27, input buses 28, 29, 30 and 31, 1 mode selection bus 32, 2 pulse generator 33 and 34, 1 element 35 with corresponding connections. 1 ye IT1

Description

The invention relates to automation and computer technology and can be used to generate control commands.

A device for generating a series of pulses containing a reference frequency generator, the first and second counting units and a trigger.

The disadvantages of the known device are low ‘accuracy of the formation of a series of pulses, low speed and narrow functionality.

The closest in technical essence to the proposed one is a device for generating a series of pulses containing a reference pulse generator, first and second counting units, a trigger, three synchronous triggers, three OR-HE elements, a third counting unit and a programmable memory unit. 20

The disadvantages of this device are the narrow functionality due to the lack of control of the duration and period of pulses in a series, as well as the duration of pauses between series of pulses of 25 owls. ''

The aim of the invention is to expand the functionality by controlling the duration and period of pulses in a series and the duration of pauses between 30 series of pulses.

This goal is achieved by the fact that in the device for generating a series of pulses containing a reference pulse generator, the output of which is connected to the input of the first trigger and to the counting input of the first conversion block, the information inputs of which are connected to the first code bus, the transfer output is to the first input of the first element 40 OR-HE, whose output is connected to the first input of the second OR-HE element, the second input of which is connected to the direct output of the first trigger and to the R-input of the second trigger, whose D-input is connected to the 45th log bus unit, C-input - with control bus, direct output - with D-input of the first trigger, second conversion unit, information inputs of which are connected to the second code bus, recording input - 50 with direct output of the third trigger, S-input of which is connected to the transfer output the second conversion block, the inverse output - with the recording input of the first conversion block, the R-input - with the output of the second element OR-HE, the third conversion block, the outputs of which are connected to the corresponding address inputs of the first programmable memory block, which controls the course of which is connected to the mode selection bus, the third element is ILINE, the output of which is connected to the output bus, the fourth trigger, the second, third and fourth programmable memory blocks, the fourth and fifth counting blocks, the fourth, fifth, sixth elements OR-HE, first and second OR elements, decoder, first and second pulse shapers, AND element, inverter, delay element, third and fourth code buses, the second input of the first OR-HE element connected to the first input of the first OR element and the inverter output, input to connected to the control bus 15 and to the first input of the fourth element

OR NOT, the second input of which is connected to the recording input of the first conversion block, the output - with the first input of the fifth OR-NOT element. the second input of which is connected to the transfer output of the fourth conversion unit, the output to the first input of the sixth element OR-NOT. the second input of which is connected to the second input of the second OR-NOT element, the output is with the R-input of the fourth trigger, the S-input of which is connected to the transfer output of the fifth conversion block, the inverse output is With the recording input of the fourth conversion block, and is connected through the first pulse shaper with the first input of the And element, the second input of which through the second pulse shaper is connected to the direct output of the third trigger and directly to the counting input of the third counting block, the output is to the counting input of the second counting block, the information inputs of which are connected to the corresponding outputs of the second programmable memory unit, and to the corresponding inputs of the decoder, the output of which is connected to the second input of the first OR element, the output of which is connected to the reset input of the third conversion unit, the outputs of which are connected to the corresponding address inputs of the second, third, and fourth programmable memory blocks, the control inputs of which are connected to the mode selection bus, Information inputs of the first recalculation block are connected to the corresponding outputs of the third programmable memory block, C-input - with C-inputs of the fourth and fifth counting blocks, information inputs of which are connected to the corresponding outputs of the fourth and fifth programmable memory blocks and, respectively, with the third and fourth code buses, and the recording input of the fifth counting block connected to the output of the second OR element, the first input of which is connected to the direct 5 1755367 6th output of the fourth trigger and through the delay element with the first input of the third element AND L AND NOT, the second input to torogo coupled to a second input of the second OR gate and the direct output of the third trig. Hera.

The drawing shows a structural diagram of a device.

The device contains a generator 1 reference pulses, the second, first, fifth and fourth counting units 2-5, the third and fourth triggers 6 and 7, the inverter 8, the second and first triggers 9 and 10, the third, first, second, fourth, the fifth and sixth elements, OR NOT 11-16, the third _; counting unit 17, second, third, first and even ^; the fourth programmable memory blocks 1821, the decoder 22, the second and first elements 23 and 24 OR, the delay element 25, the control bus 26, the output bus 27, the second, first, third and fourth input buses 28-31, the mode selection bus 32, the first and the second formers 33 and 34 pulses, element 35 I.

The device operates as follows.

In direct mode, the parameters of the pulses are set constantly on the tires 28-31 of the device. In this case, on the bus 28, the binary code of the number устанавливаетсяι is set, corresponding to the required number of pulses in the series, on the buses 29–31, respectively, the binary codes of the numbers N2, N3 and N4 are proportional to the pause duration between the series of pulses T _p , the pulse duration in the series g and the duration of the pause between pulses inside the series r _n = T - m, where T is the period of the pulses in the series. Moreover, T _p = N2 T _o , τ = N3 To and Tn = N4 To. where T _o is the pulse repetition period from the generator 1. In this case, a signal is received on the mode selection bus 32, which disconnects the outputs of blocks 18-21 from the corresponding inputs of blocks 2-5, in this mode, blocks 17-21, 22 and 24 do not affect to the operation of the device.

After turning on the power before running. In the case of a device, blocks 2 and 4 and triggers 9 and 10 are initialized by the initial setting signal (not shown). The initial state is the zero values of the signals at the direct outputs of the triggers and the transfer outputs of the conversion blocks. In this case, the outputs of blocks 2 and 4 are respectively set to the single state of triggers 6 and 7. Structurally, the counting blocks 2 -5 are made in such a way that a single signal value at the control inputs transfers the blocks to the parallel mode of writing the number, and zero to the subtraction mode by signals at the counting inputs of the blocks. Thus, a positive signal at the direct output of trigger 6 puts the blocks 2 and 4 into the mode: recording through the OR element 23, and block 3 is in the counting mode, and the signal from its transfer output is not received to the reset input of the trigger 6 before the device starts to work, 10 since it does not pass through element 12, which is covered by positive potential from the output of element NOT 8.

Similarly, the high potential from the direct output of trigger 7 puts block 4 into recording mode, the number N3 is written into it and the control signal disappears from the transfer output of block 4 to the setting input of trigger 7. Block 5 is in counting mode, but pulses from its transfer output are not received to reset the trigger. 7 through the element OR NOT 15, since the output of element 14 is a prohibiting positive potential caused by zero values of signals from the trigger 6 and control bus 26.

High potentials from the direct outputs of the triggers 6 and 7 cause the presence of low potential on the output bus 27.

The beginning of the formation of the% pulse train is determined by applying a positive potential to the control bus 26. The leading edge of the pulse on the control bus sets trigger 9 to a single state. The trailing edge of the first after this pulse from the generator 1 forms a high potential at the output of the trigger 10, resetting the trigger 9 to zero. The trailing edge of the second clock pulse from the generator 1 sets the trigger 10 to zero. Thus, when a positive control signal is applied to bus 26, a positive pulse with a duration T _o is formed at the output of trigger 10. This pulse, arriving at the input of the OR-NOT 16 element, generates (by the zero potential at its second input) a zero pulse of duration T _about . by which trigger 7 is set to zero. The positive front of the signal from the trigger 7, generates a short zero pulse at the output of the shaper 33, which, passing through the element And, is fed to the input of block 2 and writes a number into it, after which the signal is removed from the transfer output of block 2, and trigger 6 is the signal from the output element 13 is set to zero. Blocks 2 and 4 begin to work in counting mode, with block 4 counting pulses from generator 1, and block 2 from the output of block 4 (or 5, which is the same

4b the most). Blocks 3 and 5 for high potentials at the control inputs are in recording mode (numbers N2 and N4, respectively).

At the output of element 11, a positive potential appears - the first pulse of the first series is formed.

When a positive signal is applied to bus 26, a zero potential appears at the output of element 14 and thereby the operation of the OR-NOT 15 element is allowed, that is, the passage of pulses from the output of block 5 to trigger 7 · Similarly, a zero signal at the output of element Η E 8 allows the passage of signals from the output of block 3 to the reset input of trigger 6.

Upon receipt of N N clock pulses at the input of unit 4, a low potential appears at its output, which sets trigger 7 to a single state. Block 4 is transferred to the recording mode of the number N3 and generates a zero signal at the output of element 11, ’thus the formation of a pause between pulses in a series begins. In this case, block 5 is transferred to the deductible account mode.

Upon receipt of N4 pulses at the input of block 5, the zero signal from its output passes through elements 15 and 16 and sets trigger 7 to the zero state, element 11 is again brought into a single state, and a second pulse of the first series is generated, blocks 4 and 5 are translated, respectively in counting and recording modes N4, the positive edge of the signal at the inverse output of trigger 7 causes the appearance of a positive pulse at the synchro input of block 2 and reduces its content by one, fixing the end of the formation of the first pulse (together with pauses oh) the first series.

The process is repeated in this way until all the pulses of the first series have been formed. At the end of their formation, the next setting to the zero state of trigger 7 causes the appearance of a zero signal at the output of block 2, trigger 6 is set to a single state, fixing the end of the formation of the first series of pulses. Further, during the pause between series due to the zero potential at the output of trigger 6, at the output of element 11 - zero potential. The delay interval of element 25 is equal to the response time of blocks 33, 35, 2, and 6. During the formation of a pause between series of pulses, a single signal at the output of trigger 6 through element 23 supports the recording mode of block 4 and block 2, and the positive edge of this signal is converted by blocks 34 and 35 in a negative impulse and provides a record in block 2 of the value Νι.

After entering the input of block 3, converted by the zero potential from trigger 6 to the counting mode of N2 pulses, a zero potential appears at its output, setting trigger 6 through elements 12 and 13 to zero. The formation of the next series of pulses begins. Further, the operation of the device is similar to that described, and a series of pulses with the required parameters is formed at the output of element 11.

When removing the control signal from the bus 26, the device returns to its original state after the end of the formation of the next series of pulses.

If it is necessary to form a series of pulses with variable values Νι, N2, N3 and N4 for each series of pulses, a signal initializing blocks 18-21 is supplied to bus 32. In them, respectively, for each series of pulses, the values (at the same addresses) of the codes Nn, N21 are sequentially written. N31 and N41 (Information recording circuits are not shown in the drawing). After the control signal arrives on bus 26, the low potential from the output of the element NOT 8 removes the blocking potential from one of the inputs of the OR element 24. At the second input of the element 24 OR there is also zero potential, since the decoder 22 is configured to combine zero signals at its inputs, and all real series of pulses have a nonzero number of pulses. Thus, it is allowed to count the block 17, which is in the initial position in the zero state, which ensures the supply to the address inputs of the blocks 18-21 numbers corresponding to the parameters of the first series of pulses. These codes are sent to the corresponding information inputs of blocks 2-5. The device works further similarly to functioning in the described direct mode. The differences are as follows: the data arrives at the inputs of blocks 2-5 not from the input buses 28-31, but from the outputs of the blocks 18-21, initialized by the signal from the bus 32, maintained in a single (active) state throughout the entire session of the device in this mode; the end of the formation of the next series of pulses causes the formation of a short negative pulse at the output of the shaper 34, which increments the contents of block 17, setting a new address in blocks 18-21, forming the parameters of the new series of pulses, the end of the last series of pulses specified by the program leads to the appearance of '10 on the output of the block 18 of zero value (which can, for example, be entered in the corresponding cell of the program block, but), which causes the appearance of a positive signal at the output of the decoder 22, 5 set his unit 17 to the initial, zero state, then 'repeat the entire cycle pulse series defined by software.

Thus, the proposed device 10 allows the formation of a sequence of series of pulses both in direct and in program modes, adjusting both the duration of pulses within each series and 15 the duration of pauses between pulses within each series and the duration of pauses between series of pulses, which expands its functionality.

: 20

Claims (1)

SUMMARY OF THE INVENTION A device for generating a series of pulses, comprising a reference pulse generator, the output of which is connected to the input of the first trigger and the counting input 25 of the first conversion block, the information inputs of which are connected to the first code bus, the transfer output is to the first input of the first element OR NOT, the output which is connected to the first input of the second 30th element OR-HE, the second input of which is connected to the direct output of the first trigger and the R-input of the second trigger, the D-input of which is connected to the logical unit bus, C-input - with a control bus, direct 35 output - with the D-input of the first trigger, the second conversion unit, the information inputs of which are connected to the second code bus, the recording input - with the direct output of the third trigger, the S-input of which is connected to 40 ns with the transfer output of the second a counting block, an inverse output - with the recording input of the first counting block, R-input - with the output of the second OR-HE element, a third counting block, the outputs of which СО-45 are unified with the corresponding address inputs of the first programmable memory block, the control input of which is connected nen with the Mode selection bus, the third OR-HE element, the output of which is connected to the 50 output bus, the fourth trigger, and the fact that, in order to expand the functionality by controlling the duration and period of pulses in series , as well as durations of 55 pauses between series of pulses, the second, third and fourth programmable memory blocks, fourth and fifth не off-design blocks, fourth, fifth and sixth stand-up elements OR-HE, the first and second _ OR elements, decoder are introduced into it , first and second pulse shapers, electric element AND, inverter, delay element, third and fourth code buses, the second input 5 of the first element OR-NOT connected to the first input of the first OR element with the output of the inverter, the input of which is connected to the control bus and the first input of the fourth element OR INE, the second input which is connected to the recording input of the first conversion block, the output is to the first input of the fifth OR OR element, the second input of which is connected to the transfer output of the fourth conversion block, the output is from the first input of the sixth OR element NOT, the second input of which is connected nen with the second input of the second element OR NOT. the output is the R-input of the fourth trigger, the S-input of which is connected to the transfer output of the fifth conversion unit, the inverse output is connected to the recording input of the fourth conversion unit and connected through the first pulse former to the first input of element And, the second input of which through the second pulse former is connected to direct the output of the third trigger and directly with the counting input of the third counting block, the output with the counting input of the second counting block. The information inputs of which are connected to the corresponding outputs of the second programmable memory unit, and to the corresponding inputs of a decoder, the output of which is connected to the second input of the first OR element, the output of which is connected to the reset input of the third conversion unit, the outputs of which are connected to the corresponding address inputs of the second, third, and fourth programmable memory blocks, the control inputs of which are connected to the mode selection bus, the information inputs of the first recalculation block are connected to the corresponding outputs of the third programmable memory block, 0 input - with C-inputs of the fourth and fifth counting blocks, the information inputs of which are connected to the corresponding outputs of the fourth and first programmable memory blocks, respectively, with the third and fourth code buses, and the recording input of the fifth counting units are connected to the output of the second OR element, the first input of which is connected to the direct output of the fourth trigger and through the delay element to the first input of the third OR-HE element, the second input of which coupled to a second input of the second OR gate and the direct output of the third flip-flop.