SU1251174A1 - Device for controlling internal dynamic memory - Google Patents

Abstract

The invention relates to computer technology and can be used in memory devices containing a drive made on memory elements with a limited information storage time. . The purpose of the invention is to reduce -. SRI of power consumption of the device. The device for controlling dynamic dynamic memory contains a priority block 1, a sync signal block 2, a regeneration request block 3, control inputs 4 (query), 5 (reset) and 6, output 7, power input 8, delay element 9, one-shot 10 and 11, the power input 12 and the outputs 13 and 14. In the storage (regeneration) mode of the information, the supply voltage is supplied only to the nodes that generate the signals necessary to regenerate the stored information. 5 il. (L | S ate si 1

Description

one

12511

The invention relates to computing and can be used in memory devices containing a drive made on memory elements with a limited information storage time (for example, a dynamic memory on elements with a metal-dielectric-semiconductor structure), specified as a local control device. nym drive.

The purpose of the invention is to reduce the power consumption of the device,

FIG. 1 is a block diagram of a device for managing dynamic dynamic memory; Fig. 2 shows a regeneration request generation unit and a priority unit; in fig. 3 - clock unit; FIG. 4 is a time diagram of the operation of the device in the regeneration mode; in fig. 5 - time diagram of the device operation in the query processing mode (for the operation of writing a word).

FIG. 4 and 5, the numbers of diagrams, for example, the SRI correspond to the numbers of the chains or the outputs of the elements with the numbers indicated in FIG. 1-3,

The device for operational dynamic memory contains priority block 1, sync signal block 2, regeneration request generation block 3, control input 4 (request), control input 5 (reset), control, input 6, output 7, input 8 power supply, delay element 9, one and the same 10 and 11, power input 12 and outputs 13 and 14.

The priority block 1 consists of receivers 15 and 16 of the request and reset signals, element 2I-NOT-17, Schmitt trigger 18, element 2OR-NOT 19, priority trigger 20, element 2INE 21 and element 2I-NOT 22.

The unit 3 for generating a request for a regenerator; the generator contains a regeneration generator, executed on Schmitt trigger 23 and KS chain (R2, C2), and triggers 24 and 25.

Synchronous signal block 2; it includes a request signal receiver 26, trigger 27, a controlled master oscillator made on elements P HE 28-31, trigger 32, resistors and a capacitor, control signal receivers, executed on elements OR-NOT 33 and 34, the decoder operation code, performed on the element And 35, elements 36 and 37, elements

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those AND-NOT 38 and elements NOT 39 and 40, elements AND-OR-NOT 41 and 42, element AND-NOT 43, element AND-OR-NOT 44, element NOT 45, elements AND-NO 46-49 and shift registers 50 and 51.

The device for managing dynamic dynamic memory operates in the storage mode (regeneration) of information and request processing mode (word reading operation (TTS), word reading with pause, word writing (PPS), writing byte with the corresponding operation codes 00, 01, 10, 11 at inputs 6 (controls).

The device for controlling the operational dynamic memory in the information regeneration mode works as follows.

After supplying power to input 8 (main power supply) and input 12 (additional power supply), a reset signal from input 5 (reset) sets priority unit 1 to its initial state.

The regeneration request generation unit 3 generates a regeneration request signal, which in priority unit 1 sets the regeneration priority. The regeneration priority signal from priority block 1 arrives at the output 13 of the device, to delay element 9 and then to the one-shot 10 (strobe of the regenerated line), generating a reception signal and entering the line address into the dynamic-type IC during regeneration. The signal from the one-shot 10 arrives at the one-shot 11, in which para-phase regeneration pause signals are generated, blocking the priority block 1.

In the request processing mode, the request signal from input 4 (request) is sent to priority block 1 and to sync signal block 2. At the end of the regeneration process, the request signal in priority block 1 sets the channel priority. Paraphase channel priority signals are fed to the sync signal unit 2, in which the necessary sequence of control signals is generated, which is output at the device output 7. The signals .c of the outputs of the sync 2 block are fed to the priority block 1 and to the one-shot 11. The single-oscillator 11 generates channel pause signals blocking the priority block 1.

The difference in the operations performed is determined by the different duration of the signals. Write operations are characterized by

3

the presence, and the read operation, the absence of a write signal in the memory IC.

In the storage (regeneration) mode of information, the supply voltage is supplied only to the nodes that form the signals necessary for the regeneration of the stored information in the dynamic-type IC. This makes it possible to significantly reduce power consumption and improve the temperature mode of the device during long storage times.

A device for controlling on-line dynamic memory at the level of a functional circuit in the mode of registration works as follows.

When the power is turned on at input 5 (reset), a reset signal is generated, which sets the priority trigger 20 to its initial single state. The regeneration generator starts working (element 23, R2, C2). The pulses from the output of the regeneration generator arrive at the clock input of the trigger 25 and to the reset input of the trigger 24 (the trigger of the request for regeneration). On the leading edge of the positive signal at the output of the regeneration generator, the regeneration request generation unit 3 generates a regeneration request signal received at priority unit 1, in which a negative regeneration priority signal is generated when assigning a regeneration priority. The regeneration priority signal is fed to delay element 9 and the output 13 of the device and can be used to switch the address switch to transmitting the address of the regenerated line.

At the time interval defined by the delay element 9 (necessary for setting the address on the inputs of the dynamic memory IC), the one-vibrator 10 generates a signal for receiving and storing the row address in the dynamic memory IC during regeneration.

After removing the reception signal and entering the row address during regeneration, the single vibrator 11 generates paraphase regeneration pause signals. A positive regeneration pause signal at the C-input sets the trigger 24 to the zero state, and thereby the unit 3 is reset, a regeneration request is generated11. Paraphase signals of the regeneration pause block the start of block 1 of priority from the request signal at input A (request) for the duration of the pause signals of the regeneration

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generation. When the regeneration request generation unit 3 is reset, the priority unit 1 removes the regeneration priority signal.

A device for managing dynamic dynamic memory in the request processing mode when performing the CPS operation works as follows. When the LPS operation code arrives at inputs 6 (control) and the request signal is input (request) and there is no reset signal at input 5 (reset), the regeneration pause (low level) signals are blocked at the input of element 2I-NOT 17, pauses regeneration (high level) at the input of element 2IL-NOT 19, as well as the signal from the output of trigger 27 at the input of element 2I-NOT 17, the priority trigger 20 at the synchronization input is set to the zero state.

The negative signal of the regeneration pause blocks the priority block 1 from blocking during the subsequent request clock.

The trigger 27 output signal (clock trigger operation) blocks block 1 of the priority from re-triggering for long duration request sync signals upon termination of the regeneration pause signal, as well as from re-triggering for a long duration synchronization signal at the moment of the channel pause signal .

Positive and negative channel priority signals from the output of priority trigger 20 are received. respectively, the NAND 46 element, the shaper of the reception signal and the entry of the row address in the memory chip - the NAND 47 element and the input of the NAND 28 element of the controlled master oscillator, allowing its operation, as well as the Schmitt trigger 18 input , blocking the generation of the regeneration priority signal. On the leading edge of the channel priority signal on the NAND 47 element, a signal is added to enter the column address into the memory chip, and on the NAND 46 element, a signal is generated that sets the trigger 27 of the clock state to 1, confirming the permission of the control master oscillator on the second input element AND-NOT 28. Managed master oscillator generates a series of pulses, which through the element AND-NOT 31,

51

arrives at the C-input of the trigger 32 (SQ - trigger), which is often divided by two.

The phase signals from the output Eq, - the trigger 32 of the controlled master oscillator, arrive at the clock inputs of the shift registers 50 and 51, into which the necessary series of signals are formed to control the sync unit 2. On the leading edge of the signal coming from the output of the 5-shift register 51 to the NE-49 element, a reception signal is generated and the address of the column is written in the memory IC.

On the leading edge of the signals coming from the outputs 2 or 4 (depending on the operation being performed) of the register 50, the response sync signal is generated on the I-W-W-41 element. On the negative edge of the response sync signal, the signals for entering the row and column addresses into the memory chip are taken, and a negative signal front is formed on the NANDEM 46 element, on which the single-phase channel 11 pause signals are generated. On the leading edge of the signal coming from the output 1 of the shift register 50, the recording signal in the memory IC is generated on the AND-OR-NOT 42 element, and the recording signal during the byte writing operation is generated from the output from the shift register 50. A data output strobe is formed on the AND-OR-NOT element 41, which can be used to control data transceivers. Stro issuing data arrives at the elements NOT 45 and AND-NOT 48, where the response sync signal is generated. An entry strobe is formed on the AND-OR-NOT 44 element, which can be used to enter the read information into the data register.

At the end of the clock signal, the request is reset to the initial state of the work trigger trigger 27 and shift registers 50 and 51. By resetting the shift registers all the sync signals of the sync unit 2 are removed.

The operations of TTS and LPS are distinguished by the fact that at operation TTS does not produce

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A recording signal is generated on the PI-HE 43, and a data release permission signal is generated.

Claims (1)

Invention Formula five 0 five 0 15 50 five 0 five A device for managing dynamic dynamic memory containing a priority block, the first input of which is connected to the output of the regeneration request generation unit, the second input of the priority block is connected to the first input of the sync signal unit and the first control input of the device and the second input of the sync signal block are respectively the second and third control inputs of the device, the first output of the priority block is connected to the third input of the sync signal block, the first output of which is connected to the fourth input of the priority block; the fifth input of the priority block connected to the fourth input of the sync signal block; this is the first power input of the device; the second outputs of the sync signal block and the priority block are the first and second outputs of the device, respectively; This means that, in order to reduce the power consumption of the device, it contains one-shot and a delay element, the first input of which is connected to the second output of the priority block, the output of the delay element is connected to the input of the first one novibrator, the output of which is connected to the first input of the second single-oscillator, the second input of which is connected to the third output of the clock signal unit, the first output of the second single-oscillator is connected to the first input of the regeneration request generation unit and to the sixth input of the priority block, the seventh input of which is connected to the second output of the second single vibratorJ the second input of the formation block, the request for regeneration is connected to the second inputs of the delay element and the first one-shot, to the third input of the second one-shot and to the second input the priority block and is the second power input of the device. puf3 114 20 JrLr rLrLS J J- (riel rLn-TLTL (pua.B