SU1513525A1 - Device for monitoring storage - Google Patents

Abstract

The invention relates to computing and can be used to control random access memory devices. The purpose of the invention is to increase the reliability of the control. The device contains an EXCLUSIVE OR 1 element, an error detection block 2, a shift register 3, a trigger 4, a prohibition element 5, a counter 6, N switches 7, an AND 8 element, a delay element 9, logical formers "0" 10 and logical "1" 11 , (N + 1) -th switch 12. 5 Il.

Description

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1513525

The invention relates to a computational technical test and can be used in the control of random access memory devices, g

The purpose of the invention is to increase the reliability of the control.

Fig. 1 is a block diagram of a memory control device; on

Element AND 8 provides synchronization of the error block of the error detection unit 2 only during the reading of information from the monitored memory, and delay element 9 delays the synchronization pulses. 2 - the element of the ban; in FIGS. 3, a unit for the sampling time of the error detection controller; Figs. 4 and 5 show timing diagrams of the operation of the device while monitoring a memory device containing four memory elements.

The device contains an element ISKGOO-CHAU1CH, ITS OR 15 block 2 error detection, register 3 shift, thr ger 4, prohibition element 5, counter 6, group of cohortors 7, element I 8, element 9 delayed constructor 10 logical O, driver 11 logical, switch 12, element 13, trigger 14, element I 15, elements of ICGN CHA1 1EE 1SH 16, element AND - NOT 1.7 and 18, trigger 19,

The device works as follows

The relay of the formation of a pseudo-random cyclic sequence (FIG. 4) is provided by supplying the device 1 with a logical 1 and connecting the inputs of the PCM element to the RZHI 1 to the outputs of the bits of the shift register 3 through the inputs of the cohorticator group 7, the required polynomial being specified using switches 7, which connect the required outputs of the bits of the shift register 3 to the inputs of the UPDATE OR 1 element. The formation mode of the regular sequence (Fig. 5) is provided by inputting the task

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memory. As a result, at the output of the error detection block 2, logical 1 is formed if a discrepancy between the recorded and read information occurs. In fig-. 5 depicted

timing charts of the device in the formation of a regular sequence.

Element 5 of the ban works in the following way. When a resistive 1 is applied to its input, the synchronization pulse passes to the synchronization input of register 3, and the device forms a pseudo-random cyclic sequence. And when the logical O input is applied to this input, the blocking does not occur and the device generates a p-HJTO control sequence.

Error detection unit 2 operates as follows. The synchronization input of block 2 receives the synchronization pulses, which through the element AND-H 18 arrive at the synchronization input

35 trigger 19, which is in the zero state. The reference information is fed to one of the inputs of each logical element EXCLUSIVE OR 16, and information from the corresponding output of the controlled memory is fed to the other. If the information does not match, a logical O is formed at the output of the logical element ISKHAOCh10b HER OR 16, and at the output of the element NANDA17 - logical

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35 flip-flop 19, which is in the zero state. The reference information is fed to one of the inputs of each logical element EXCLUSIVE OR 16, and information from the corresponding output of the controlled memory is fed to the other. If the information on the output of the logical element ISKHAOCh10E HER OR 16 does not match, a logical O is formed, and the output of the NAND 17 element is formed

reldama device E logical O

and connecting the outputs of the bits of the register; which translates trigger 19 into

1, on the inverse of 3 shift to the inputs of the element 1 using the switches 7 as follows; one of the switches-7 connects the output of the i-ro register bit 3 to one of the inputs of element 1, the other switch 7 connects the output of element 11 of logical 1 to the other input of element 1, and the remaining inputs of element 1 connect the other switches 7 to the shaper 55 10 logical O.

After the clock pulse devices are fed to the synchronization input, the device is

At the trigger output 19, a logical O is generated, which prohibits the posting of pulses to the trigger synchronization input of the trigger 19, thereby preventing the trigger from returning to a logical O state with a positive control of the next element of the memory.

Claims (1)

Invention Formula A memory control device containing the item EXCLUSIVE OR, The system will monitor the memory, record and read the regular sequence. Element AND 8 provides for synchronization of the error block of the error detection unit 2 only during reading information from the monitored memory, and delay element 9 delays the synchronization pulses by the sampling time of the controller 0 five memory. As a result, the logical error 1 is generated at the output of the error detection unit 2 if a discrepancy between the recorded and read information occurs. In fig-. 5 depicted timing charts of the device in the formation of a regular sequence. Element 5 of the ban works in the following way. When applying a resistive 1 to its input, the synchronization pulse passes to the synchronization input of register 3, and the device forms a pseudo-random cyclic sequence. And when the logical O is applied to this input, the lock does not occur and the device generates a p-HJTO control sequence. Error detection unit 2 operates as follows. The synchronization input of block 2 receives synchronization pulses, which through the element AND-NOT 18 arrive at the synchronization input 5, trigger 19, which is in a zero state. One of the inputs of each logical element EXCLUSIVE OR 16 receives reference information, and the other - information from the corresponding output of the controlled memory. If the information does not match, a logical O is formed at the output of the logical element ISKHAOCh10b HER OR 16, and at the output of the element NANDA17 - logical 0 0 state of logic At the output of trigger 19, a logical O is generated, which prohibits the arrival of pulses at the trigger input of trigger 19, thereby preventing the trigger from returning to the state of logic: O when the control of the next memory element is positive. Invention Formula A memory control device containing the item EXCLUSIVE OR, error detection unit, shift register, trigger, prohibition element, element output counter EXCLUSIVE OR connected to the input of the shift register, one of whose bits is connected to the first input of the error detection unit and is the device data output, the input group of the error detection unit is data inputs of the device, the transfer output of the counter is connected to the transfer input of the prohibition element and the enable input of the trigger, the inverse output of which is connected to the input of the recording permission of the prohibition element, the synchronization input to It is the device's synchronization input and is connected to the synchronization inputs of the trigger and the counter, which is due to the fact that, in order to increase the control accuracy, a group of switches is entered into the device the outputs of the shift register, the element And, the delay element, the switch, the outputs of the switches of the group are connected. With the corresponding inputs of the INSERT element OR, the shift register outputs are connected to the first information inputs of the corresponding group switches, the second and third information inputs of which are the first and second inputs of the device mode setting, the permission input of the prohibition element is the third input of the device mode settings, the outputs of the count1-sh: a are connected to the information inputs of the switch group and are the address inputs of the device, the direct output of the trigger is connected to the first input of the element nta and is the output of the resolution device, the second input element And is connected to the output of the delay element, the input of which is connected to the synchronization input of the device, the output of the element And is connected to the synchronization input the error detection unit, the control input of the switch is connected to the synchronization input of the device, the information input of the switch is connected to the output of the inhibit element, the output of the switch The ra is connected to the input, synchronizing the shift register, the output of the error detection block is the output of the monitoring result of the device. fig.g  T nJTJTJTJTJTJTJ-LJTJ-L. g L L. / fJJ-1 P  P ----- ruiLnjiJTJTJTJTjarb FIG. L L. P  P