SU1589280A2 - Device for checking digital units - Google Patents

Abstract

The invention relates to computing and may find application in the development of devices for autonomous and embedded control of digital devices. The aim of the invention is to increase the reliability of the device by eliminating the false triggering of the comparator unit and increasing the reliability of monitoring the digital blocks by calculating the number of identical cycle parameters. A second memory block, a counter, a switch, the third and fourth elements OR the second element AND, the third, fourth, fifth delay elements and a single pulse shaper are entered into the device. 1 il.

Description

 The invention relates to computing, can be used in the development of devices for autonomous and embedded control of digital devices and is in addition to auth. No. 127885A.

The purpose of the invention is to discover the reliability of the device by eliminating the false triggering of the comparison unit and increasing the reliability of monitoring the digital blocks by increasing the number of identical cycle parameters.

The drawing shows a functional diagram of the device. .

A device for controlling digital blocks contains a unit 1 modulo-two adders, a shift register 2, a controllable block 3, a combinator, an adder 4, a result register 5, a generator of 6 clocks, the first element And 7, a counter of 8 clocks,

an address counter 9, a first memory block 10, a comparison block 11, a cycle number counter 12, a first 13 delay elements, a trigger 14, a first 15, a second 16 IL elements, a second delay element 17, a second memory block 18, a third element OR 9 , the third delay element 20, the second element AND 21, the fourth 22, the fifth 23 delay elements, the counter 24, the switch 25, the single pulse shaper 26, the fourth element OR 27, the start input 28, the first 29, the second 30 control inputs, information inputs 31, output 32 of the health signal, output 33 of the fault signal.

The device works as follows.

Preliminarily, in memory block 18, it is written in an additional form — the least number of cycle parameters that is unacceptable under control;

WITH

70

D 30

 TO)

. the number of maximally possible identical values of parameters for the entire period of contol is indicated. At the same time, the parameter itself and the number of its repetitions should be stored at the same addresses of blocks 10 and 18 of memory, respectively. Record in block 18 is as follows. On the counter 9 of the address o, the write address is formed in block 18 (the write and control circuits to the counter 9 are not shown) At the input of mode 30 sets a single-level signal allowing output 15 to the input of switch 25 of information from inputs 31. At inputs 31, information dp recording to block 18. A recording signal is received from input 29 of the recording strobe through element 20 OR 19 (at its second input, a zero level signal; output of comparison unit 11 in zero state) to the recording input of memory block 18.

- The signal at the start 28 input sets the initial value in the counter of the 12 number of cycles, resets the counter 2A to the zero state and, the pass through the OR 15 element, sets the initial states of the shift register 2, the counter of 8 clocks, resets to zero neither register 5, address meter 9 and trigger 14. Same signal, delayed by delay 13 delay

At the time of bringing the device to the initial state, it sets the trigger 14 to one. The delay element 13 is necessary for the delay of signals coming from generator 6 to the time the device is reset. In the absence of element 13, an asynchronous start of elements of the device is possible due to different installation times of elements 2, 3 and 5 and 7. The signal from the direct output of trigger 14 opens element 7 and pulses from the output of generator 6 are transmitted through element 7 to the synchronization inputs of the shift register 2 , controlled block 3, register 5 and counter 8 cycles. The clock pulses generate the operation of an autonomous generator consisting of a shift register 2, a controlled block 3 and a block 1 modulo two.

From the output of the register 2 shift code combinations arrive at the inputs of the controlled block, to the input of the block

five

0

five

0

five

0

five

I adders modulo two and to the input of the combinational adder A, Reaction of the controlled block. 3 at the input action comes from the output of the controlled block to the second group of inputs of the block 1 modulo-two adders. The output signals of block 1 modulo-two adders participate in the formation of a new value of the shift register bits.

The combination adder A, together with the register 5, accumulates the sum of binary numbers from the output of the shift register 2. The number of cycles of operation of the autonomous generator is determined by the counter capacity of 8 cycles, the pulse from the overflow output of which sets the trigger 14 to the zero state, which interrupts the flow of clock pulses into the device blocks. The overflow pulse of the counter 8 clocks simultaneously passes through the OR element 16 and through the delay input element 17 of the readout of blocks 10 and 18 to the input of the imager 26, which generates a short pulse whose leading edge is delayed relative to the output pulse of the element 17 for transients in block 10 memory, With the output of the shaper 26 impulse arrives at. Comparison input of block 11. This allows comparing the numbers received in the first and second groups by the input of comparator 11. At this time, the first group of inputs of the comparison unit 11 contains a number, and the second group contains the input of the comparison unit II as a cycle meter pair contained in the zero cell of the memory unit 10, since the address counter 9 at this moment has a zero value. If there is a discrepancy between the numbers coming in from the two groups of inputs of the block AND the comparison, the signal from the output of the block noncomparison 1 1 enters the summed input of the counter 9 of the address and increases its contents by one. The same signal, transmitted through the OR element 16 and delayed by the delay element 17 at the time of setting the new address, allows comparison of the number with the contents of the next cell of the memory block 10.

If the number does not coincide with any of the parameters recorded in the cells of memory block 10, then the overflow pulse of the address counter 9, sent through the fourth element OR 27 to output 33, indicates a malfunction of the monitored unit.

When the obtained number coincides with the contents of one of the cells of the memory block 10, the signal from the output of the matching unit 11 of the comparison is fed to the summing input of the counter 12 of the number of cycles and to the second input of the OR 15 element, thus restarting the device to the new test cycle. At the same time, this signal arrives at the first input of the second element I 21, the second input of which receives the readout of memory blocks delayed by the delay element 20 from the output of the element 17, through which information from block 18 is read. Information on the information inputs of counter 24 comes from signal c The output of element I 21 is written in parallel to counter 24, after which the contents of counter 24 are incremented by -il (at a signal from the output of element And 21 delayed by element 22 of the delay) and through open through the second inputs of the switch. 25 (at the input of the mode 30 at this time a signal of the zero level) is fed to the information input of the memory unit 18. At the same time, the signal from the output of the delay element 22 through the delay element 23 and the third element OR 19 (at its first input is a zero level signal) is fed to the recording input of the unit 18, which records information at the address set at the output of the counter 9.

The restart of the device generally occurs when another

the memory, increased by +1 in the counter 24, will form at the overflow output a signal, which arrives at output 33 and indicates a malfunction. Address, i.e. the parameter by which the looping occurs can be determined at the output of the counter 9. If during each cycle of checking the corresponding number of signals coincides with the contents of the cells of the memory block 10, then the overflow signal of the counter 12 of the number of cycles received at the output 32 with a large

J5 credibility says about the health of the object control. The simultaneous generation of a signal at outputs 32 and 33 indicates a malfunction of the monitored block or a regular reading of the same cycle parameter, which is hardly possible with this control method.

saapfl-zf jaa .. ga.zl.1 ZyZ-ep-I - delay on the corresponding elements, the control of the digital block ends with the appearance of a signal at output 32 or (and) 33.

Claims (1)

Invention Formula thirty Digital control device blocks auth.St. No. 1278854, characterized in that, in order to increase the reliability of the device by eliminating the false triggering of the comparator unit and increasing the reliability of monitoring the digital blocks by calculating the number of identical cycle parameters, a second memory unit is inserted into the device 35 counter, second, AND element, switch, third and fourth IS elements, third, fourth, fifth delay elements and forma tion from a well-known initial state of the jitter pulse, the output of which of the unit being connected by parameter. In this case, in block 18, the increment information by +1 is recorded at another 50. goma address. However, in the event of a malfunction of the monitored block or apparatus of this device, it may be that the cycle parameter does not exit from the zone, it is regularly compared with one of the cells of block 10, for example, only one or two, which indicates a malfunction in the apparatus . Then for several re-launches the contents of a certain cell 55 with the output of the comparison unit, and the input with the output of the second delay element, the read input of the second memory block and the input of the third delay element, the output of the third delay element of the soydan with the first input of the second element And the second input connected to the first input of the first element OR, the output of the second element H is connected to the installation input of the counter and through the fourth element of the delay to the counting input of the counter, and through the fifth element of the delay is connected to the first the memory, increased by +1 in the counter 24, will form at the overflow output a signal, which arrives at output 33 and indicates a malfunction. Address, i.e. the parameter by which the looping occurs can be determined at the output of the counter 9. If during each test cycle the corresponding number coincides with the contents of the memory cells of the memory block 10, then the overflow signal of the counter 12 of the number of cycles arriving at output 32 is large credibility says about the health of the object control. The simultaneous generation of a signal at outputs 32 and 33 indicates a malfunction of the monitored unit or a regular reading of the same cycle parameter, which is hardly possible with this method of control. saapfl-zf jaa .. ga.zl.1 ZyZ-ep-I - the delay on the corresponding elements, the control of the digital unit ends with the appearance of a signal at output 32 or (and) 33. Invention Formula Digital control device blocks auth.St. No. 1278854, characterized in that, in order to increase the reliability of the device by eliminating the false triggering of the comparator and increasing the reliability of monitoring the digital blocks by calculating the number of identical cycle parameters, a second memory block is inserted into the device the counter, the second, the AND element, the switch, the third and the fourth IS elements, the third, the fourth, the fifth delay elements, and the forma tion of the pulse j, the output of which is connected 50 55 with the output of the comparison unit, and the input with the output of the second delay element, the read input of the second memory block and the input of the third delay element, the output of the third delay element of the soydan with the first input of the second element And the second input connected to the first input of the first element OR, the output of the second element H is connected to the installation input of the counter and through the fourth element of the delay to the counting input of the counter, and through the fifth element of the delay is connected to the first the input of the third OR element, the second input of which is connected to the first input of the recording strobe of the device, and the output is connected to the recording input of the second memory block, the group of address inputs of which is connected to the group of the bit outputs of the address counter, the group of information inputs of the second memory block a group of switch outputs, a group of outputs of the second memory block is connected to a group of information inputs of the counter, the reset input of which is connected to the device start input, a group of outputs the counter is connected to the first group of information inputs of the switch, the second group of information inputs and the control input of which are connected respectively to the group of information inputs and the device mode input, the overflow output of the counter is connected to the first input of the fourth OR element, the second input of which is connected to the address overflow output The output of the fourth element is the failure output of the device. J2