SU1341683A1 - Device for checking read-only memory - Google Patents

Abstract

The invention relates to computing. The purpose of the invention is to simplify the device. The device contains a generator of I pulses, a local control unit 2, an element OR 9, a counter of 10 addresses, a modulo control unit 12, a comparison unit 13, an AND 15 element, a NOT 16 element, a single-bit memory block 17, a register 21. In the device the fault signal is corrected by the information recorded in block 17, so that it is possible to bypass the required number of addresses in the monitored block of permanent memory, 1 slug. from 4 O5 00 with

Description

13

The invention relates to computing.

The purpose of the invention is to simplify the device.

The drawing shows a block diagram of a device for monitoring fixed memory blocks.

The device contains a pulse generator 1, a local control unit 2 consisting of start 3 and trigger 3, element 4 and element 5, start input 6, external stop input 7, distributor 8 pulses, element 9 and counter 10 addresses. The device is connected to the monitored memory block 11 and contains a modular control block 12, a comparison block 13, an end address input 14, an AND 15 element, a HE element 16, a one-bit memory block 17, an information input 18, a control input 19, a clock input 20 and register 21.

The device works as follows;

Before starting the device, it is necessary in block 17, the volume of which is not less than the volume of the controlled block 11, to record the initial information. The essence of the initial information is that units are recorded at the addresses at which information is not scanned in the block 11 being checked.

The recording is made as follows.

The input 20 receives the action signals necessary for the operation of the counter 10 connected to block 17, the information input of which receives the sequence O. and 1, and the control input 19 receives the recording signals.

Upon completion of the recording of the initial information, the device is ready for operation.

After the signal arrives at the input 6, the pulses of the generator 1 through the block 2 and the dispenser 8 of the clock pulses arrive at the inputs of the monitored block 11, and through the OR 9 element to the input of the counter 10, which performs the function of the address resolver.

The information from the monitored unit 11 read through this address through the register 21 enters unit 12 of the control modulo. The result of the control goes to one of the inputs of the element I 15, to the other input of which the information comes from block 1 7,

32

tanna at the same address. The signal 1, read from block 17, through the element NOT 16 enters the input of the element and 1 5 and ensures its blocking. At that, the result of monitoring information read from the tested block 11, generated at the output of block 12 and gated by a pulse from the distributor 8 sync pulses, does not flow through AND 15 and the OR element 5 to the trigger input 3. Therefore, the device does not stop control at the following address.

The signal O., read from block 17, through the element NOT 16 enters the input of the element and ensures the passage of the malfunction signal produced by block 2, through the element 15 and element 1 XI 5 to the input of the trigger 3, setting it to a position that blocks the passage of generator pulses 1 through the element I4 to the distributor of 8 clock pulses, the fault is stopped.

Automatic stopping of the device upon reaching the final address of the monitored unit 11 is provided by generating a stop signal of the comparison unit 13 supplied to the monitored unit 11 and the final address of the control input to input 14. The stop signal from the output of the comparison unit 13 goes through the OR 5 element to the reset input of the trigger 3 .

Claims (1)

Invention Formula A device for monitoring a fixed memory, comprising a pulse generator, a local control unit, a pulse distributor, a comparison unit, an address counter, a register, an AND element, the output of the pulse generator connected to a clock input of a local control unit, the output of which is connected to a synchronous input pulse distributor, the first output of which is the output of the control reading the device, the second and third outputs of the pulse distributor are connected respectively to the first input of the element AND and the controlling, the input of the cp unit The inputs, start and stop inputs of the local control unit are respectively the device start input and the stop input by an external device signal, the address counter output is the device address output, the register input is the first information input of the device, characterized in that, in order to simplify the device , a one-bit memory block, a modulo control unit, a NOT element and an OR element, the first input of which is a clock input of the device, the second input of the OR element is connected to the fourth the output of the pulse distributor, the output of the OR element is connected to the counting input of the address counter, the output of the register is connected to the information input of the control unit modulo, the control input of which is connected to the fifth output of the pulse distributor, the output of Or L.Pcholinsk 4441/55 Compiled by V.Fokina Tehred L.Serdyukova Co Pod Circulation 589 VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab ,, d.4 / 5 Production and printing company, Uzhgorod, Projecto st., 4 The control unit is connected to the second input of the AND element, the third input of which is NOT connected to the output of a single-bit memory block whose address input is connected to the output of an address counter, the information input and the write-read input of a single-bit memory block are respectively the second information input and the control input of the device, the first input of the comparison block is the input of the final address of the device, the second input of the comparison block is connected to the output of the address counter, the output of the comparison block is connected to the input at the stop at the end of the control signal of the local control unit, and the stop input at the fault signal is connected to the output of the element I, Proofreader A.Zimokosov Subscription