JPH0787045A - Multi-frame pattern detection circuit - Google Patents

Abstract

PURPOSE:To reduce the coincides return time of a frame pattern by forming a multi-frame pattern in a complete form based on a sub-frame. CONSTITUTION:The circuit is provided with n-sets of frame pattern detection sections 3-1 to 3-n comparing a sub-frame pattern from a frame pattern extract section 1 with a predetermined sub-frame pattern from frame pattern generating sections 2-1 to 2-n to detect a multi-frame pattern, an OR gate 4 Oring output signals of the frame pattern detection sections 3-1 to 3-n to output an output, and also with a protection circuit section 5 receiving an output signal of the OR gate 4 to take protection over a predetermined number of stages and using the result for a multi-frame coincidence output, and a reset pulse generating section 6 detecting a leading or a trailing of the output signal of each of the frame pattern detection sections 3-1 to 3-n to generate a pulse used to reset the protection circuit section 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-frame pattern detection circuit, and more particularly to a circuit for detecting a multi-frame pattern in a data signal in a transmission device or the like and detecting the protection to detect the multi-frame pattern. It is a thing.

With the increase in reliability and quality of transmission equipment, a multi-frame pattern composed of a plurality of frame patterns is used instead of a single frame pattern to synchronize the transmission side and the reception side. Therefore, a circuit for detecting the multi-frame pattern in this case is required.

[0003]

2. Description of the Related Art FIG. 16 shows a conventional configuration example of such a multi-frame pattern detection circuit.
Is a frame pattern generation unit that generates a frame pattern according to the frame timing pulse FP1, 12 is a frame pattern extraction unit that extracts a frame pattern in the received data according to the frame timing pulse FP1, 13 is a frame timing pulse FP1 and a frame pattern generation unit 11, and A frame pattern detection unit that detects a frame pattern from each output signal of the frame pattern extraction unit 12 and outputs a pulse B indicating the first frame, and 14 is a predetermined N according to the output signal of the frame pattern detection unit 13 and the frame timing pulse FP2. This is a protection circuit unit that protects the stages and outputs a frame pattern coincidence detection pulse A.

The operation of this multi-frame pattern detection circuit will be described below with reference to the time charts of FIGS.

First, the frame pattern generator 11 generates a frame pattern by using a frame timing pulse FP1 generated from a well-known means (not shown) and also generates a pulse (shown by *) indicating the beginning of the frame pattern. It is sent to the frame pattern detection unit 13.

Further, the frame pattern extraction unit 12 extracts a frame pattern from the received data by using the frame timing pulse FP1 and also the frame pattern detection unit 13
Send to.

Then, in the frame pattern detector 13,
By comparing the frame pattern extracted from the received data with the frame pattern from the frame pattern generation unit 11, it is detected whether or not they match. Further, the frame pattern detection unit 13 outputs a pulse B indicating the first frame.

The result is the frame timing pulse FP
After confirming N protection stages in the protection circuit unit 14 using 2, the reliable pattern matching detection is performed, but in the example of FIG. 17, the output of the frame pattern detection unit 13 indicates the pattern mismatch, and then the forward protection is performed. After passing only the stage N, the pulse A changes from the pattern matching state (H level) to the pattern mismatching state (L level).
Has changed to.

Further, as shown in FIG. 18, when the pattern matching is detected, the pulse A is changed from the pattern non-matching state (L level) to the pattern matching state (H level) via the protection of the rear N stages from the time when the pattern matching is detected. Is changing.

[0010]

However, since the frame pattern output from the frame pattern generation unit 11 has one type of cycle, hunting occurs when a pattern mismatch occurs, but one multi-frame occurs when there is a shift of one subframe. It takes hunting time for the frame, and protects the rear side to achieve the pattern matching state. Therefore, the pattern matching recovery time becomes long.

In other words, since there is only one frame pattern generation unit and one frame pattern detection unit, it is not possible to quickly search for a frame pattern, which causes a problem that it takes time to restore the pattern coincidence.

Therefore, it is an object of the present invention to provide a multi-frame pattern detection circuit which can shorten the frame pattern coincidence recovery time.

[0013]

[Means and Actions for Solving the Problems] [1-1]
Means for clarity (1): FIG. 1 In order to achieve the above object, the multi-frame pattern detection circuit according to the present invention constructs a multi-frame from received data by frame timing pulses as shown in principle in FIG. A frame pattern extraction unit 1 that extracts n (n is a natural number of 2 or more) subframe patterns, and n that generates n predetermined subframe patterns that are sequentially displaced from each other by one subframe by a frame timing pulse. Of the frame pattern generation units 2-1 to 2-n, the subframe pattern from the frame pattern extraction unit 1 and the predetermined subframe pattern from the frame pattern generation units 2-1 to 2-n. N frame pattern detection units 3-1 to 3-n for detecting the multi-frame pattern,
An OR gate 4 that outputs the logical sum of the output signals of the frame pattern detection units 3-1 to 3-n, and the OR gate 4
Of the output signal of each of the frame pattern detection units 3-1 to 3-n and the protection circuit unit 5 that outputs the output signal as a multi-frame coincidence output. A reset pulse generator 6 for detecting and generating a pulse for resetting the protection circuit unit 5 is provided.

In the above case, each frame pattern detecting section 3-1 to 3-n can output a pulse indicating the detection of the leading subframe pattern via the OR gate 7.

Further, the protection circuit section 5 can reset each frame pattern detection section 3-1 to 3-n to prevent hunting when a subframe pattern mismatch is detected by the output signal of the OR gate 4. it can.

[1-2] Action of the present invention (No. 1): FIG.
4 to put it simply, the present invention has a frame pattern generation unit and a frame pattern detection unit for n subframes, so that all the subframe patterns are always monitored and detected by each frame pattern detection unit. By doing so, the pattern matching recovery time can be shortened because the frame pattern of the sub-frame is always detected by one of the n frame pattern detecting units. Since the rear protection is immediately started without hunting, the pattern matching return time can be shortened also from this point.

Hereinafter, this will be described in detail with reference to FIGS. The waveforms shown in parentheses in these figures are used in the examples described later.

First, the frame pattern extraction unit 1 extracts a sub-frame pattern in received data by using the frame timing pulse FP1 to detect a frame pattern detection unit 3-1.
~ Send to 3-n.

Further, n frame pattern generators 2-1
.About.2-n generate n predetermined subframe patterns which are sequentially shifted by one subframe from each other by the frame timing pulse FP1.

That is, the frame pattern generation unit 2-1 generates a predetermined frame pattern from the first subframe to the nth subframe of the multiframe, and the frame pattern generation unit 2
-2 is from the second sub-frame to the n-th sub-frame and the first
The frame pattern of the subframe is generated, and the last frame pattern generation unit 2-n similarly generates the frame pattern of the nth subframe to the (n-1) th subframe (see FIG. 2).

The frame pattern detectors 3-1 to 3-n are
The sub-frame patterns from the frame pattern extraction unit 1 and the frame patterns from the respective frame pattern generation units 2-1 to 2-n are compared with each other, and if they match each other, the H level is set. If they do not match, the L level (or vice versa is also possible). ). As a result, the output of one frame pattern detection unit is always at H level, and the other is at L level (see FIG. 3).

Preferably, one of the frame pattern detecting units 3-1 to 3-n outputs pulses a to x indicating the first sub-frame of the multi-frame when the patterns match. Then, a pulse B indicating the first frame is generated via the OR gate 7.

The output signals of the frame pattern detectors 3-1 to 3-n are ORed by the OR gate 4 and then sent to the protection circuit unit 5. In the protection circuit section 5, 06 is an OR gate 4.
The frame pattern detection result is obtained by detecting a predetermined number of protection steps, and a pattern matching detection pulse A is output.

In this case, as shown in FIGS. 3 and 4, the protection circuit section 5 does not take the number of protection stages from when the output of the OR gate 4 shows the pattern matching of the H level, but rather from the reset pulse generation section 6. The number of protection steps is taken when the reset pulse is exhausted.

That is, the reset pulse generator 6 receives the detection results from the respective frame pattern detectors 3-1 to 3-n and uses the rising edge (or falling edge) of the pulse to reset the reset pulse (1 A pulse having a clock width) is generated and output to the protection circuit unit 5.

By this reset pulse, even if the same frame pattern is extracted from the frame pattern extraction unit 1, resetting the protection circuit unit 5 prevents the pattern matching state. In the example of FIGS. 3 and 4, the protection circuit unit 5 starts the protection operation only when the output pulse of the frame pattern detection unit 3-4 detects the pattern coincidence, and outputs the pattern coincidence detection pulse after a predetermined number of protection stages. ing.

The protection circuit unit 5 outputs the pulse C to reset the frame pattern detection units 3-1 to 3-n when the power supply is turned off and the patterns are not matched, so that hunting does not have to be performed. It is preferable to immediately put it in the rear protection.

[2-1] Means of the present invention (No. 2): FIG. 5 In the present invention, as shown in principle in FIG. 5, n frames in the present invention (No. 1) shown in FIG. Instead of the pattern generating units 2-1 to 2-n, one frame pattern generating unit 2 and n-1 number of frame patterns generated from the frame pattern generating unit 2 are sequentially shifted by one subframe from each other. N for generating a predetermined subframe pattern
-1 adder circuits 20-1 to 20-n-1 are used.

[2-2] Action of the present invention (No. 2): FIG.
8 is, to put it simply, the present invention provides n-1 adder circuits for adding n-1 subframe patterns to one frame pattern generating unit to generate n subframe patterns. By having n number of frame pattern detectors, all the subframe patterns are always monitored and detected by each frame pattern detector, so that one of n frame pattern detectors always detects the subframe. Since the pattern match recovery time can be shortened because the frame pattern is detected, and in the case of pattern mismatch such as when the power is turned on, the rear protection immediately starts without hunting. Can be shortened.

This will be described below with reference to FIGS. 6 to 8. The waveforms shown in parentheses in these figures are used in the examples described later.

First, the frame pattern extraction unit 1 extracts the sub-frame pattern in the received data by using the frame timing pulse FP1 to detect the frame pattern detection unit 3-1.
~ Send to 3-n.

Further, one frame pattern generator 2 generates a frame pattern of the first sub-frame to the n-th sub-frame by the frame timing pulse FP1 to generate a frame pattern detector 3-1 and n-1 adder circuits. 20
-1 to 20-n-1.

In the adder circuit 20-1, the frame patterns from the frame pattern generating section 2 are sequentially shifted by one subframe to generate the frame patterns of the second subframe to the nth subframe and the first subframe. To do. Further, the adder circuit 20-2 generates a frame pattern of the third subframe to the second subframe.
Similarly, the final adder circuit 20-n-1 generates a frame pattern from the nth subframe to the (n-1) th subframe (see FIG. 6).

In this way, the n predetermined sub-frame patterns generated by the frame pattern generator 2 and the adder circuits 20-1 to 20-n-1 and sequentially shifted from each other by one sub-frame are the frame pattern extractor 1. The sub-frame patterns from are compared with each other, and if they match, the H level is set, and if they do not match, the L level is set (or vice versa).

The following operation is the same as that of the example of the present invention (No. 1) shown in FIGS. 3 and 4, as shown in FIGS. 7 and 8, and therefore its explanation is omitted.

[3-1] Means of the Present Invention (Part 3): FIG. 9 In the present invention, as shown in principle in FIG.
Instead of the n frame pattern generation units 2-1 to 2-n shown in FIG. 1, one frame pattern generation unit 2 for generating n predetermined subframe patterns sequentially shifted by one subframe from each other is used. ing.

[3-2] Action of the present invention (No. 3): FIG.
0 to FIG. 12 In short, the present invention has n frame pattern generating units and n frame pattern detecting units that generate frame patterns of different n types of subframe periods, so that all subframe patterns are always maintained. By monitoring and detecting each of the frame pattern detecting units, the frame pattern of the subframe is always detected by any one of the n frame pattern detecting units, so that the pattern matching recovery time can be shortened. In addition, since the rear protection is immediately started without hunting when the patterns do not match when the power is turned on, the pattern matching return time can be shortened from this point as well.

This will be described below with reference to FIGS. The waveforms shown in parentheses in these figures are used in the examples described later.

The frame pattern extraction unit 1 extracts the frame pattern in the received data using the frame timing pulse FP1 and sends it to the frame pattern detection units 3-1 to 3-n as in the above case.

On the other hand, the frame pattern generator 2 generates n multi-frame patterns which are offset by one sub-frame from each other. That is, the frame pattern generation unit 2 includes a multiframe pattern from the first subframe to the nth subframe, a second subframe to the nth subframe, and a first subframe.
Multiframe patterns up to subframes, similarly, finally, multiframe patterns from the nth subframe to the (n-1) th subframe are sequentially generated and given to the frame pattern detection units 3-1 to 3-n respectively (see FIG. 10).

The following operation is the same as that of the example of the present invention (No. 1) shown in FIGS. 3 and 4, as shown in FIGS. 11 and 12, and therefore its explanation is omitted.

[0042]

EXAMPLE [1] Example of the present invention (No. 1): FIG.
2 and 3 In this embodiment, in the principle diagram shown in FIG. 1, the lower 2 bits of each sub-frame forming a multi-frame are
The frame pattern extraction unit 1 extracts four types of frame patterns by changing the values to “00”, “01”, “10”, and “11”. In addition, four frame pattern generators 2-1 to 2-4 and four frame pattern detectors 3-1 to 3-4 are provided in accordance with this. In addition, the frame pattern extraction unit 1 to each of the frame pattern detection units 3-1 to 3-4, together with the frame patterns extracted from the received data, read pulse necessary for reading these frame patterns (in FIGS. 13 and 2). (Illustrated by *)
Is occurring.

The frame pattern generators 2-1 to 2-4 are composed of counters, which generate subframe patterns 00 → 11, 01 → 00, 10 → 01, 11 → 00, respectively, and generate subframe patterns of the subframe patterns. A pulse indicating the beginning (indicated by * in FIGS. 13 and 2) is output and given to each frame pattern detection unit 3-1 to 3-4.

In the frame pattern detection units 3-1 to 3-4, the frame pattern from the frame pattern extraction unit 1 and the frame patterns from the counters 2-1 to 2-4 are compared with each other. If there is a mismatch, L
It has a level. As a result, the output of one frame pattern detection unit is always at the H level, and the other outputs are at the L level.

Further, each frame pattern detector 3-1 to 3
At -4, pulses a to d indicating the first subframe of the multiframe are generated at the time of pattern coincidence detection. Pulses a to d indicating the detection result of each frame pattern detection unit 3-1 to 3-4 and the first subframe of the multiframe
Is a pulse C output from the protection circuit unit 5 (see FIG. 3)
Controlled by.

This pulse C validates each frame pattern detection unit 3-1 to 3-4 at the time of detecting the pulse coincidence, and the result of the frame pattern detection unit 3-1 to 3-4 at the time of detecting the pulse disagreement at the time of power-on. And inhibit the pulse output indicating the first sub-frame of the multi-frame.

The reset pulse generator 6 is composed of a differentiating circuit, receives the detection results 1 to 3 from the frame pattern detectors 3-1 to 3-4, and uses the rising edge (or the falling edge) to make 1 A reset pulse having a clock width is generated (see FIG. 3).

The reset pulse from the reset pulse generating section 6 is output to the protection circuit section 5 as described above, and even if the same frame pattern is temporarily extracted from the frame pattern extracting section 1, it is completely subframed. By resetting the protection circuit unit 5 until a pattern match is detected, incomplete pattern match state is avoided.

The protection circuit section 5 uses the frame timing pulse FP2 (see FIG. 3) to detect the detection results of the frame pattern detection sections 3-1 to 3-4 and obtains five protection steps forward and backward. , Pattern coincidence detection is performed and a pattern coincidence detection pulse A is output.

Further, each frame pattern detector 3-1 to 3
The pulses a to d indicating the first sub-frame of the multi-frame from -4 are ORed by the OR gate 7, and the pulse B indicating the first sub-frame of the multi-frame is output in the pattern matching state.

[2] Embodiment of the present invention (Part 2): FIG.
4, FIG. 6 and FIG. 7 In this embodiment also, in the principle diagram shown in FIG.
Similar to the embodiment of FIG. 13, the lower 2 bits of each subframe of the multiframe are “00”, “01”, “10”,
The frame pattern extraction unit 1 is assumed to change to “11”.
Extract four types of frame patterns, and read pulses necessary for the frame pattern detection unit 2 (see FIGS. 14 and 6).
(Indicated by * in the figure) is generated and sent to each of the four frame pattern detection units 3-1 to 3-4.

The frame pattern generator 2 provided with only one is composed of a counter for generating 00 → 11, and the three adder circuits 20-1 to 20-3 have the output value "11" of the counter 2. ], And add 01 → 00,
10 → 01, 11 → 00 subframe patterns are generated, and a pulse (indicated by * in FIGS. 14 and 6) indicating the beginning of the subframe patterns is output to output each frame pattern detection unit 3-1 to 3-3. Give to -4.

In the frame pattern detecting units 3-1 to 3-4, the frame pattern from the frame pattern extracting unit 1, the frame pattern generating unit 1 and the adding circuits 20-1 to 20-3 are included.
The frame patterns from 1 to 3 are compared with each other, and if they match, the H level is output, and if they do not match, the L level is output.

Others are the same as in the embodiment of FIG. 13 and FIGS. 2 and 3, as shown in FIGS. 6 and 7,
The description is omitted.

[3] Embodiment of the present invention (Part 3): FIG.
5, FIG. 10 and FIG. 11 Also in this embodiment, in the principle diagram shown in FIG.
Similar to the embodiment of FIG. 13, the lower 2 bits of each subframe of the multiframe are “00”, “01”, “10”,
The frame pattern extraction unit 1 is assumed to change to “11”.
Extracts four types of frame patterns, generates necessary read pulses (indicated by * in FIGS. 15 and 10) for the frame pattern detection units 3-1 to 3-4, and sends them to each.

One shift register is used as the frame pattern generator 2, and frame patterns P1 to P4 (00 → 11, 01) sequentially shifted by one sub-frame period are used.
→ 00, 10 → 01, 11 → 00) and indicates the beginning of the subframe pattern P1 * to P4 *
(See FIGS. 15 and 10) is output and given to each frame pattern detection unit 3-1 to 3-4.

In the frame pattern detectors 3-1 to 3-4, the frame patterns from the frame pattern extractor 1 and the frame patterns P1 to P4 from the frame pattern generator 2 are used.
Are compared with each other, and if they match, an H level output is given, and if they do not match, an L level output is given.

Others are the same as those of the embodiment shown in FIGS. 13 and 14, as shown in FIGS. 10 and 11, and the description thereof will be omitted.

[0059]

As described above, according to the multi-frame pattern detection circuit of the present invention, the frame patterns are generated by the number of sub-frames forming the multi-frame and these frame patterns are extracted from the received data. By comparing with the frame pattern, the multi-frame pattern is always detected in perfect form based on the sub-frame, so the recovery time until pattern matching detection can be shortened, and it is possible to reduce It greatly contributes to reliability and quality improvement.

Further, in the pattern mismatch detection state such as when the power is turned on, the detection of the frame pattern can be stopped so that the hunting does not have to be performed.
In such a case, the backward protection is immediately put into effect, so that it is possible to further shorten the recovery time until the pattern matching is detected.

[Brief description of drawings]

FIG. 1 is a block diagram showing a principle configuration of a multi-frame pattern detection circuit (No. 1) according to the present invention.

FIG. 2 is a time chart diagram (1) for explaining the operation of the multi-frame pattern detection circuit (No. 1) according to the present invention.

FIG. 3 is a time chart diagram (2) for explaining the operation of the multi-frame pattern detection circuit (No. 1) according to the present invention.

FIG. 4 is a time chart diagram (3) for explaining the operation of the multi-frame pattern detection circuit (No. 1) according to the present invention.

FIG. 5 is a block diagram showing a principle configuration of a multi-frame pattern detection circuit (No. 2) according to the present invention.

FIG. 6 is a time chart diagram (1) for explaining the operation of the multi-frame pattern detection circuit (No. 2) according to the present invention.

FIG. 7 is a time chart diagram (2) for explaining the operation of the multi-frame pattern detection circuit (No. 2) according to the present invention.

FIG. 8 is a time chart diagram (3) for explaining the operation of the multi-frame pattern detection circuit (No. 2) according to the present invention.

FIG. 9 is a block diagram showing a principle configuration of a multi-frame pattern detection circuit (No. 3) according to the present invention.

FIG. 10 is a time chart diagram (1) for explaining the operation of the multi-frame pattern detection circuit (No. 3) according to the present invention.

FIG. 11 is a time chart diagram (2) for explaining the operation of the multi-frame pattern detection circuit (No. 3) according to the present invention.

FIG. 12 is a time chart diagram (3) for explaining the operation of the multi-frame pattern detection circuit (part 3) according to the present invention.

FIG. 13 is a block diagram showing an embodiment of a multi-frame pattern detection circuit (No. 1) according to the present invention.

FIG. 14 is a block diagram showing an embodiment of a multi-frame pattern detection circuit (No. 2) according to the present invention.

FIG. 15 is a block diagram showing an embodiment of a multi-frame pattern detection circuit (part 3) according to the present invention.

FIG. 16 is a block diagram showing a configuration of a conventional example.

FIG. 17 is a time chart (1) for explaining the operation of the conventional example.

FIG. 18 is a time chart (2) for explaining the operation of the conventional example.

[Explanation of symbols]

 1 frame pattern extraction unit 2, 2-1 to 2-n frame pattern generation unit 20-1 to 20-3 addition circuit 3-1 to 3-n frame pattern detection unit 4, 7 OR gate 5 protection circuit unit 6 reset pulse Generation unit In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (5)

[Claims] 1. A frame pattern extraction unit (1) for extracting n (n is a natural number of 2 or more) subframe patterns constituting a multiframe from received data by a frame timing pulse, and one subframe each by a frame timing pulse. N frame pattern generators (2-1 to 2-n) that generate n predetermined sub-frame patterns that are sequentially displaced by the number of frames
And detecting the multi-frame pattern by comparing the sub-frame pattern from the frame pattern extraction unit (1) with the predetermined sub-frame pattern from the frame pattern generation units (2-1 to 2-n). Frame pattern detectors (3-
1 to 3-n) and an OR gate (4) for taking the logical sum of the output signals of the frame pattern detection units (3-1 to 3-n), and outputting the output signal of the OR gate (4). The protection circuit unit (5) that inputs and protects a predetermined number of stages and outputs the result as a multi-frame coincidence output and the rising or falling of the output signal of each frame pattern detection unit (3-1 to 3-n). A multi-frame pattern detection circuit, comprising: a reset pulse generator (6) for detecting and resetting the protection circuit (5). 2. The n frame pattern generators (2-1)
.. 2-n) instead of one frame pattern generator (2) and n-1 predetermined numbers sequentially shifted from the frame patterns generated by the frame pattern generator (2) by one subframe. N to generate a subframe pattern
The multi-frame pattern detection circuit according to claim 1, wherein one adder circuit (20-1 to 20-n-1) is used. 3. The n frame pattern generators (2-1)
~ 2-n), instead of generating n predetermined sub-frame patterns that are sequentially displaced from each other by 1 sub-frame 1
2. The multi-frame pattern detection circuit according to claim 1, wherein one frame pattern generation unit (2) is used. 4. Each frame pattern detection unit (3-1 to 3-)
n) is a pulse indicating the detection of the first subframe pattern
4. The multi-frame pattern detection circuit according to claim 1, wherein the multi-frame pattern detection circuit outputs the signal via an R gate (7). 5. When the protection circuit section (5) detects a subframe pattern mismatch based on the output signal of the OR gate (4), each frame pattern detection section (3-1 to 3−).
5. The multi-frame pattern detection circuit according to claim 1, wherein n) is reset to prevent hunting.