JPS61108238A - Frame synchronizing circuit - Google Patents

Abstract

PURPOSE:To eliminate the processing time except the time required substantially for synchronous locking and to decrease the restoring time from the locking time and out of synchronism by providing the number of consecutive coincidence count means in response to the bit number for a large frame and a synchronization check means. CONSTITUTION:A frame synchronizing circuit consists of a bit synchronizing circuit 1, a timing pulse generator 14, consecutive coincidence counter circuits 20, 30, 40, synchronizing check circuits 60, 70, 80 and an OR circuit 15. For example, the circuit 20 consists of an AND circuit 21, coincidence detection circuits 22A, 22B, 22C (hereinafter A, B, C are omitted), a dissidence detection circuit 23, a counter 24, and a synchronizing pattern generating circuit 25. Thus, the synchronizing bit is detected by applying consecutive coincidence count for a large frame's share. That is, in case of a 3-bit synchronizing pattern, three kinds of synchronizing patterns subject to phase shift and a received code series are subject to consecutive coincidence count at the same time. Thus, even when the synchronizing patterns are received in any order, the synchronizing bit is extracted by using the consecutive coincidence countmeans 20, 30, 40 for a large frame's share to generate a frame trigger pulse.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is capable of always extracting synchronization bits and outputting frame trigger pulses by simply counting consecutive coincidences of received code sequences for one large frame and checking synchronization. The present invention relates to a frame synchronization circuit configured as described above.

[Conventional technology]

Conventionally, in a frame synchronization circuit, one large frame (
N bits) are multiple (n) small frames (r bits)
, and in a large frame, n bit synchronization pulses are regularly spaced at (r-1) bit intervals, l b
As a means for detecting and synchronizing the above-mentioned so-called transcendental arrangement type frame pattern, which is transmitted from the transmitting side by transposing it one by one, on the receiving side, there is generally a 1-bit shift frame synchronization method and a 1-bit shift frame synchronization method. No. 58-1986
There is a method of frame synchronization circuit No. 08.

Next, using a diagram, we will explain the 1-bit shift type frame synchronization circuit (referred to as the first prior art) and the patent application No. 58-19860.
The operating principle of the method shown in No. 8 (referred to as the second prior art) is shown below.

FIG. 4 is a block diagram of this type of 1-bit shift type frame synchronization circuit, and FIGS. 0 to 5 are waveform diagrams showing the state of FIG. 4. First, the digital code series 9 having the configuration shown in FIG. 5, transmitted from the transmitting side, is supplied to the bit synchronization circuit 1 shown in FIG. This bit synchronization circuit 1 has a clock pulse 13 synchronized with the basic clock cycle of the digital code series.
(Extract the clock pulse 13 in Figure 5 (g) and
The signal is supplied to the frame counter 2 via the bit delay circuit 7 and the AND circuit 8. This frame counter 2 is composed of a counting circuit and the like, and is incremented by clock pulses. When the frame counter 2 reaches a predetermined count, it generates a decoder timing pulse and outputs it to the output terminal 12.

Furthermore, the frame counter 2 supplies a decoder timing pulse to the AND circuit 5.6 via the transmission line 10.

The AND circuit 5 uses the decoder timing pulse to
The code (time slot) at the time of synchronization on the receiving side is selected from the digital code series and output to the mismatch detection circuit 4. A
The ND circuit 6 shapes the decoder timing pulse using the clock pulse supplied from the bit synchronization circuit 1 via the AND circuit 8 in order to stabilize the operation of the circuit, and outputs it to the synchronization pattern generation circuit 3. This synchronization pattern generation circuit 3 is composed of a counting circuit and the like, and is a circuit that generates synchronization patterns "1" to "9" shown in FIGS. The output is supplied to a mismatch detection circuit 4.

The mismatch detection circuit 4 compares the code (time slot) at the time of synchronization on the receiving side in the digital code series output from the AND circuit 5 and the synchronization pattern output from the synchronization pattern generation circuit 3. During normal synchronization, the digital code sequence output from the AND circuit 5 and the synchronization pattern match, so normal operation continues; when out of synchronization,
The AND circuit 6 erroneously selects a digital code series, and the mismatch detection circuit 4 generates a pulse every time there is a mismatch and outputs it to the 1-bit delay circuit 7.

The 1-bit delay circuit 7 shifts the synchronization pattern by 1 bit, and delays the pulse output from the mismatch detection circuit 4 by one cycle of the clock pulse supplied from the bit synchronization circuit 1, and is used as an inhibition circuit. AN that can be done
Output to D circuit 8.

Further, the AND circuit 8 is used in conjunction with the 1-bit delay circuit 7 to shift the synchronization pattern by 1 bit, and when the 1-bit delay circuit 7 is outputting a pulse, the clock pulse supplied from the bit synchronization circuit 1 is When there is no pulse output from the 1-bit delay circuit 7, a clock pulse is supplied to the t-AND circuit 6 and the frame counter 2 during normal operation. By repeating the shifting process at the time of mismatch several times in this way, the synchronized state is restored from K.

50-5 are waveform diagrams showing state transitions in the synchronization pull-in process by the circuit of FIG. 4. “0” of digital code series 9
” is in the synchronized state, and now it is assumed that the state is “C” in Figure 5, where one bit is out of synchronization.If the synchronization pattern cannot be detected in this state, the next state is “2”, Figure 5, 0. If it can be detected, it passes through N/n bits and returns to the state "1".
” and repeats this process to return to the synchronized state “
9” synchronous pull-in occurs at the fifth time (8).

This first prior art sequentially searches for a synchronization pattern while shifting one bit, so when the synchronization pattern is shifted by one bit, such as "1", the synchronization pattern is shifted by r×N (small frame), and the number of It is necessary to compare synchronization patterns for (large frames). This has the disadvantage that the time required to acquire synchronization is inevitably long, and this circuit can only be used for lines with low error rates, few out-of-sync lines, or lines for which it is acceptable to take some time to acquire synchronization. There was a problem.

Next, Japanese Patent Application No. 58-198608 (second prior art)
Figure 6 shows the operating principle of the frame synchronization circuit shown in Figure 6.
It is shown in FIG.

The configuration of the second prior art is such that in a frame synchronization circuit that forms a frame trigger that has a period consistent with a dog frame made up of a plurality of n small frames and is synchronized with a superordinately arranged frame pattern, each of the small frames is mating pulse forming means for respectively forming n time slots having a width of a synchronization pattern of frames and mutually shifted in phase within the large frame; Compare the fixed synchronization patterns and when they match for each time slot, count the number of matches, output a matching pulse when the counted value reaches n, and output a reset pulse when they do not match. It is characterized by comprising: r coincidence counting means for outputting, and a synchronization detection means for extracting the time slot in which these coincidence counting means output the coincidence pulse and using it as the frame trigger.

FIG. 6 is a block diagram of the second prior art, and FIGS. 7-7 are operation waveform diagrams of each part in FIG. In this embodiment, a clock pulse 13 is generated from a received digital code string 9 (Fig. 7).
4, and timing pulses 16, 17.1 whose phase is shifted by the number of small frames (3) from this clock pulse 13 ((2) in FIG. 7).
8 (FIG. 7 (D)) and three consecutive coincidence counting circuits 20, 30, 40 that detect coincidence with each synchronization pattern (FIG. 7 (D)) in each small frame. and these consecutive coincidence counting circuits 20.30°4
Three synchronization test circuits 60, 70, 80 temporarily hold each output of 0, and these synchronization test circuits 60, 70.
80.

Further, the continuous-number construction circuit 20 is connected to an AND circuit 21 and -
A number output circuit 22, a discrepancy detection circuit 23, and a counter 2
4 and a synchronization pattern generation circuit 25 that generates a predetermined synchronization pattern (r01 in FIG. 7), and the other continuous-number construction circuits 30 and 40 have similar constructions. The synchronization check circuit 60 is composed of a set/reset flip-flop 61 and an AND circuit 62, and the other synchronization check circuits 70 and 80 have the same configuration. 13 is supplied to the timing pulse generation circuit 14, the timing pulse generation circuit 14 outputs the continuous coincidence counting circuit 20.30.
．． The phase-shifted timing pulses 16, 17, and 18 are outputted to the AND circuits 21, 31, 41 of 40, and the ANDs 62, 72, 82 of the synchronization check circuit 60, 70, 80, respectively. The AND circuit 21 (31, 41) takes the AND of the timing pulse 16 (17, 18) and the received digital code sequence 9, and calculates the -number construction circuit 22 (32, 4).
2) and the mismatch detection circuit 23 (33, 43) in FIG.
The extracted data 26 (36, 46) shown in [F] is output.

- The number output circuit 22 (32, 42) receives each synchronization pattern r011J 27 (37, 47) output from the synchronization pattern generation circuit 25 (35, 45) and the output from the AND circuit 21 (31, 41). Extracted data 26
(36, 46) and if they match, the matching pulse 28 (38, 48) shown in FIG.
4, 44).

On the other hand, the mismatch detection circuit 23 (33, 43) ANDs the synchronous pattern r011J 27 (37, 47) output from the synchronous pattern generation circuit 25 (35, 45).
Extracted data 2 output from circuit 21 (31, 41)
6 (36, 46), and if they do not match, a mismatch pulse 29 (39, 49) shown in FIG. 70 is output to the counter 24 (34, 44).

The counter 24 (34, 44) is composed of a counting circuit, and the clock pulse 13 supplied from the bit synchronization circuit 1.
, and counts the coincidence pulses 28 (38, 48) from the minus number construction circuit 22 (32, 42), and when a predetermined count number (count 2 in the example shown in FIG. 7) is reached, the synchronization starts. Set/reset flip-flop 61 (71, 81) of test circuit 60 (70, 80) Overflow pulse 242 (342, 442) (Outputs the output shown in FIG. 7 (g). In this case, the overflow pulse 242 output by the counter is input to the set input of the set-reset flip-flop 61, and is input to the reset input for the set-reset flip-flop 70 knobs 71.81.The overflow pulse 342 output by the counter 34 is input to the set input of the set-reset flip-flop 710. input, set-reset flip-flop 61
．． 81, it is input to the reset input and the counter 44
The over7o-pulse 442 outputted by is input to the set input of the set-reset flip-flop 81, and is input to the reset input for the set-reset 7 rib 70 tube 61.71.

Furthermore, when the counter 24 (34, 44') is counting and a mismatch pulse 29 (39, 49) is output from the mismatch detection circuit 23 (33, 43), this counter is reset.

The synchronization pattern generation circuit 25 (35, 45) generates the synchronization pattern 27 (37, 47) according to the count number of the counter 24 (34, 44).
2, 42) and the mismatch detection circuit 23 (33° 43). In the case shown in FIG. 7, the synchronization pattern is 3 bits 1011", 011" is one cycle, and the count number of the counter 24 (34, 44) is 0 → 1 → 2 → 3.
→ 4 → 5... When counted, synchronization pattern 27 (3
7, 47) outputs 0→1→1→0→1→1... In other words, since the synchronization node is 3 bits, it outputs 0'0'' only when the count number is an integral multiple of 3, and outputs 1 for any other count number.

The set/reset flip-flop 61 (71, 81) of the synchronization check circuit 60 (70, 80) is connected to the counter 24.
The set-reset flip-flop 61 (71, 81) is set or reset by the -flow pulse 242 (342, 442) output from (34, 44).

In FIG. 7, the synchronization pulse inserted in time slot "2" M2R, Jll in the received digital code sequence 9 is synchronized with the synchronization pattern 37 output from the synchronization pattern generation circuit 35, so that the counter 34 When the count becomes the largest, an overflow pulse 342 is output. The overflow pulse 342 from this counter 34 sets the reset flip 70 knob 71.
is set and its output goes from '0'' to '1''. In addition, the set/reset flip 70 tabs 61 and 71 are reset by the automatic flow pulse 342, and each output becomes 0''.
is set reset 7 rib 70 knob 61 (71°81)
The logical product of the output pulse and the timing pulse 16 (17, 18) from the timing pulse generation circuit 11 is taken and outputted to the OR circuit 15.

In FIG. 7, the set-reset flip-flop 6
1, 71.81, the output of one (71) is '1' and the output of the other (61, 81) is On, so the timing pulse 17 output from the timing pulse generation circuit 14 is output from the OR circuit 15 as the output of the AND circuit 72.At this time, the output of the AND circuit 62.82 is @031, so the timing pulse 17 is output to the output 19 of the OR circuit 15, and this pulse becomes the timing pulse for the decoder.

As explained above, the second conventional technique differs from the method of the first conventional technique in which synchronization is pulled in while sequentially shifting the phase of the synchronization pattern, in that the received digital code sequence for one dog frame is counted for continuous coincidence. Since the synchronization pattern is detected from the time slot where the count value exceeds a predetermined threshold, there are fewer operations to compare matches and mismatches.
Detection time can be significantly reduced.

[Problems to be solved]

However, in the situation shown in Figure 7, the synchronization pattern generator output ro11J on the receiving side and the synchronization pattern inserted into the received code sequence start with rol1J, and the phases of both coincide, so one large frame is generated. It was possible to extract the synchronization bits using the synchronization checking means, but the synchronization bits inserted in the received code sequence did not start with rollJ, but were out of phase and started with "110..." or rlo
If it starts with IJ (see Figure 3 of the present invention), it is not possible to extract the synchronization bit by counting consecutive coincidences for one large frame and checking the synchronization, but it is not possible to extract the synchronization bit by counting consecutive coincidences for one large frame and checking for consecutive coincidences for two or more dog frames. The disadvantage is that it requires synchronization.

The reason for this is that the consecutive coincidence counting means counts the consecutive coincidences of the received code series only in the order of rollJ of the synchronization pattern generation circuit output.

Therefore, the phase of the synchronization pattern included in the first large frame of the received code sequence is
riio...'' or rlolJ, the synchronization bit cannot be extracted using one dog frame of the first received code sequence. The fact that synchronization bits cannot be extracted from the received code sequence for one first large frame brings about the following problems.

(2) In general, when synchronizing a synchronization pattern that is superimposed in a digital code series, there is a probability that data will be mistakenly determined to be a synchronization bit, and this probability can be expressed in the form Φ1. Here, K is the number of bits of the synchronization pattern arranged in a transcendental manner. Therefore, if the number of bits K of the synchronization pattern is increased, the probability of erroneous synchronization will also be reduced. Therefore, in general, a larger number of synchronization bits than the three bits used in the embodiment of this patent is often used.

In that case, the period for one large frame also becomes longer, so the time spent on synchronization pull-in also becomes longer.

■ Similarly, when synchronization is broken, it takes longer to restore synchronization.

■ If the transmission speed of the digital code series is low, the time required for synchronization acquisition and return will be longer.

Means for Solving Problem c] The present invention solves the above problem, and the present invention solves the above problem.
In a frame synchronization circuit that generates a frame trigger that has a cycle that matches nXr=N bits and is synchronized with a superordinately arranged frame pattern, the large frame (
timing pulse forming means for forming n phase-shifted time slots each having a width of a synchronization pattern, an input signal in each of the n time slots, and n types of phase shifts; When these match for each time slot, the number of matches is counted, and when the counted value reaches n (L threshold), a match pulse is output. When they do not match, n×r coincidence counting means output a pulse to reset the coincidence counting circuit, and the time slots in which these coincidence counting means output the coincidence pulses are extracted and the time slots are extracted from the frame. The present invention is characterized in that it includes a synchronization check means that is used as a trigger.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to FIGS. 1 to 3.

FIG. 1 is a block diagram of an embodiment of the frame synchronization circuit according to the present invention, FIGS. Figures 1 and 2
It is a figure which shows the synchronization pattern for explaining a figure.

In the figure, the frame synchronization circuit includes a bit synchronization circuit 1 that extracts a clock pulse 13 from a received code sequence 9, and timing pulses 16 and 17 whose phase is shifted from this clock pulse 13 by the number of time slots constituting a small frame. ．．
A timing pulse generator 14 forming a timing pulse 18, a three-system continuous-number counting circuit 20 (30, 40) that detects coincidence between data extracted by the timing pulses 16, 17, and 18 and synchronization patterns having different phases. , three synchronization test circuits 60, 70, and 80 that temporarily hold the respective outputs of the three systems of continuous-number counting circuits, and these synchronization test circuits 60.
, 70.80.

In addition, the continuous-several sheet output circuit 20 (30, 40) is an
D circuit 21 (31, 41), - several sheet output circuit 22A,
22B, 22C (33A, 33B, 33C, 4
3A, 43B.

43C) and mismatch detection circuits 23A, 23B, 23
C (33A.

33B, 33C, 43A, 43B, 430) and counter 24A.

24B, 24G (34A, 34B, 34C, 44A,
44B, 44C) and phase-shifted synchronization patterns rlJ, r2J as shown in FIG.

Synchronous pattern generation circuits 25A, 25 that generate "3"
B.

25C (35A, 35B, 35C, 45A, 45
B, 45C).

Furthermore, the synchronization check circuit 60 (70, 80) includes a set-reset flip-flop 61 (71, 81), and a
It is composed of an ND circuit 62 (72, 82).

Next, the operation will be explained. First, the timing at which the receiving side started receiving the code sequence sent from the transmitting side is
It is assumed that the numbers start from 3 in FIG.

When the received code series 9 (FIG. 2a) is input to the bit synchronization circuit 1, a clock pulse 13 synchronized with the basic clock pulse period of the received code series is output to the timing pulse generation circuit 14. The timing pulse generation circuit 14 is
Each AND circuit 21 (31, 41) of the continuous-number counting circuit 20 (30, 40) and the synchronization check circuit 60 (70, 8
Timing pulses 16 (17, 18) (Fig. 2 (
E), (J), (0)).

The AND circuit 21 (31, 41) takes the logical product of the timing pulse 16 (17, 18) and the received code sequence 9, and outputs - several output circuits 22A, 22B, 22C (32
A.

32B, 32C, 42A, 42B, 42C).

(a) Coincidence detection circuits 22A, 22B, 22C (32A,
32B, 320° 42A, 42B, 420) is a synchronization pattern generation circuit 25A.

25B, 25C (35A, 35B, 35C, 45
Figure 3 output from A, 45B, 45C) @~0
Synchronization pattern "1".

r2J, r3J, AND circuit 21 (31,4
Compare the extracted data output from 1) and if they match,
Coincidence pulse 28 shown in Fig. 2 (G), (L), (■)
A, 28B, 28C (38A, 38B, 38C
, 48A, 48B, 48C) to the counter 24A,
24B, 24C (34A, 34B, 34C, 44
A, 44B.

44C).

On the other hand, the mismatch detection circuits 23A, 23B, 23C (3
3A.

33B, 33C, 43A, 43B, 43C) are synchronous turn generation circuits 25A, 25B, 25C (3
5A, 35B, 35C, 45A, 45B.

45C). Synchronization pattern rlJ in Figure 3
, r2J, r3J and AND circuit 21 (31,4
Compare the extracted data output from 1), and if there is a discrepancy, compare the unmatched data 29A, 29B, 29C (39A, 3) shown in Figure 2 (9), CM), (R).
9B, 39C, 49A, 49B.

49C) to the counters 24A, 24B, 24C (34
A, 34B.

34C, 44A, 44B, 44C).

Counters 24A, 24B, 24C (34A, 34
B, 34C.

44A, 44B, 44C) are composed of counting circuits, -number calculation circuits 22A, 22B, 22C (32A,
32B, 32C, 42A.

42B, 42C) coincident pulses 28A, 28B
, 28C (38A, 38B, 38C, 48A,
48B, 480), and when a predetermined count number (in the example shown in FIG. 2, every count 3) is reached, O
Overflow pulses 242A, 242B, 242C (342A,
342B, 342C, 442A, 442B, 44
20) (Outputs Figure 2 (T).

The OR circuit 243 (343, 443) outputs an over 7 four-pulse 244 to the set/reset flip 70 knob 61 (71, 81) of the synchronization check circuit 60 (70, 80).
(344, 444) (Outputs Figure 2 (G).

In this case, the overflow H-pulse 244 output by the OR circuit 243 is input to the set input of the set-reset flip-flop 61, and to the reset input for the set-reset flip-flop 71.81. Also O
The overflow pulse 344 output by the R circuit 343 is input to the set input of the set-reset flip-flop 710, and to the reset input for the set-reset flip-flop 61.81. In addition, the OR circuit 44
The overflow pulse 444 output by the set-reset flip-flop 810 is input to the set input of the set-reset flip-flop 810, and the overflow pulse 444 output by the set-reset flip-flop 70 is input to the reset input of the set-reset flip-flop 70.

In addition, counters 24A, 24B, 24C (34A,
34B.

34C, 44A, 44B, 44C) are counting, the discrepancy detection circuits 23A, 23B, 23C (
33A, 33B, 33C.

43A, 43B, 43C) to mismatched pulse 29A
, 29B.

29C (39A, 39B, 39C, 49A, 49
B, 490) is output, this counter is reset to O.

Synchronous pattern generation circuits 25A, 25B, 25C (3
5A.

35B, 35C, 45A, 45B, 450) is the counter 24A.

24B, 24C (34A, 34B, 340.44
A, 44B, 44C) synchronization pattern 27A, 27B depending on the count number.

27C (37A, 37B, 37C, 47A, 47
B, 47C) FIG.
, 32C, 42A, 42B, 42C) and mismatch detection circuits 23A, 23B, 23C (33A, 33
B, 33C, 43A.

43B, 430).

In the case shown in Figure 3, the synchronization pattern is 3 pins) ro
Let llJ be one period, and synchronization patterns rlJ, r2J.

"3" generates a phase-shifted synchronization pattern, respectively.

Counters 24A, 24B, 24C (34A, 34
B, 34C.

44A, 44B, 440) count number from 1 to 2
→ 3 → 4 → 5 → 6... As shown by the synchronized turns rlJ, r2J, r3J in Figure 3,
Synchronous pattern generation circuit 25A (35A, 45A)
3) outputs the synchronization pattern "O-+l→1→0→1→1..." of the intermediate period pattern "1". The synchronization pattern generation circuit 25B (35B, 45B) generates the synchronization pattern "1→1→" of the synchronization pattern "2" in FIG.
0→1→1→0..." Full output. Synchronous pattern generation circuit 25C (35C.

45C) outputs the synchronization button "1→0→1→1→0→1..." of the synchronization pattern "3" in FIG. 30.

That is, in the embodiment according to the present invention, since the synchronization pattern is 3 bits, three types of phase-shifted synchronization pattern generation circuits 25A, 25B, and 25C (35A, 35B) are used.

35C), (45A, 45B, 450).

The set/reset flip-flop 61 (71, 81) of the synchronization check circuit 60 (70, 80) is connected to the OR circuit 24.
3 (343, 443) to set or reset the set/reset flip-flop 61 (71, 81).

In FIG. 2, the synchronization pulse inserted in the received code sequence 9 (0 in FIG. 2) has the code number 5°8.11.1.
7.20, r 110110 J is inserted, and this inserted synchronization pattern and the synchronization pattern 47B output from the synchronization pattern generation circuit 45B (Fig. 2 [F
] are synchronized, so when the count number of only the counter 44B becomes the sharpest and the count number reaches "3", the overflow pulse 442B (Fig. 2 (T
) is output.

overflow pulse 442 from counter 44B with
B is an OR circuit 443 that performs a logical sum with the output signals of the counters 44A and 44C, and inputs an output signal 444 to the set/reset flip-flop 81. Once entered,
The output 811 (FIG. 2(U)) of the set-reset flip-flop 81 changes from "0" to "1". Further, the set/reset flip-flops 61, 71 are reset by the overflow pulse 444, and each output becomes "0". Further, the AND circuit 62 (72, 82) performs the logical product of the output pulse of the set/reset flip 70 knob 61 (71, 81) and the timing pulse 16 (17, 18') from the timing pulse generation circuit 11, and outputs the output pulse to the OR circuit 15.
Output to.

In FIG. 2, the set-reset flip-flop 6
Since the output of one of the flip-flops 61.71 (81) is "1" and the output of the other flip-flop 61.71 is "0", the timing pulse 18 output from the timing pulse generation circuit 14 is It is output from the OR circuit 15 as the output of the AND circuit 82.

At this time, the outputs of the AND circuits 62 and 72 are "0", so the timing pulse 18 of the timing pulse generation circuit 14 is output as the output signal 19 of the OR circuit 15 (M in FIG. 2), and this pulse is the received code. This becomes a frame trigger pulse for decoding the series.

Note that the overflow pulse output from the counter is
This is a signal for determining synchronization/asynchronous, and the count number (threshold) for outputting an overflow pulse is set to "3" in this embodiment, but if the number of bits of the synchronization pattern changes (if it is 9 bits), It is necessary to set the count number to a value corresponding to "9" or more.

As explained above, in the first prior art, the time required to acquire synchronization in a badly out-of-synchronization state in order to detect a synchronization bit is n (number of bits of synchronization pattern) x time equivalent to one large frame. However, the present invention improves the method of continuous coincidence counting using a fixed synchronization pattern shown in the second prior art. The synchronization bit can be detected by counting consecutive matches for one large frame. In other words, the present invention does not count consecutive matches of received code sequences using fixed synchronization patterns as in the past, but because it is uncertain in what order the synchronization patterns inserted in the received code sequences will be received. As shown in Figure 3, in the case of a 3-bit synchronization pattern, there are three ways to receive the synchronization pattern, so continuous coincidence counting of the three phase-shifted synchronization patterns and the received code sequence is performed simultaneously. . As a result, as shown in the present embodiment, no matter what order the synchronization patterns are received, the continuous coincidence counting means for one large frame can extract the synchronization bit and generate the frame trigger pulse. I can do it.

Note that even if the received code sequence has some errors due to the influence of the line, the set/reset flip 7
1 (71, 81), the synchronized state can be maintained.

However, in this example, in order to simplify the explanation, 3
Although a bit longer synchronization pattern was used, generally longer synchronization patterns are used.

Furthermore, when this synchronization pattern is composed of 3 bits, data other than the synchronization bits and the synchronization pattern generation circuit 25A,
25B, 25C (35A, 35B, 35C, 4
5A.

45B, 45C) have a possibility of occurring at a certain time with a synchronization pattern. However, it is obvious that this can be easily avoided by checking the consecutive number of received code sequences for two or more large frames.

〔Effect of the invention〕

As explained above, according to the present invention, (number corresponding to the number of bits of the synchronization pattern) x (number corresponding to the number of bits of the small V-frame) (for example, a synchronization button is 3 bits, a small frame is 3 bits). If it is composed of bits, 3X3=9)=
Since a means for continuously counting the number of bits corresponding to the number of bits for one large frame and a means for checking synchronization are provided, processing time other than the time essentially required for synchronization pull-in is unnecessary. Therefore, the pull-in time and the time required for recovery in the event of loss of synchronization are also shorter than in the past.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of a frame synchronization circuit according to the present invention, FIGS. 2(A) to (5) are diagrams showing state transitions of the above circuit, and FIGS. 3(A) to (D ) are shown in Figure 1, respectively.
FIG. 4 is a block diagram of a 1-bit shift type frame synchronization circuit, which is the first prior art, and FIGS. FIG. 6 is a block diagram of a frame synchronization circuit which is the second prior art, and FIG. 7(A) is a waveform diagram showing the state transition of the circuit.
-(J) are waveform diagrams showing state transitions of the circuit shown in FIG. 6, respectively. 1...Bit synchronization circuit 2...FuV-mukau:
/II3... Synchronization pattern generation circuit 4... Mismatch detection circuit 5, 6.8... AND circuit 7... 1-bit delay circuit 10... Transmission line 11.
・Reception code input terminal

Claims (1)

[Claims] A frame trigger that has a period that matches a large frame (n x r = N bits) consisting of multiple (n) small 7 frames (r bits) and is synchronized with a synchronization pattern (n bits) arranged in a transcendental manner. a frame synchronization circuit that forms n time slots each having a width of the synchronization pattern of each of the small frames and whose phase is shifted from one another in the large frame; The input signals in each of the n time slots are compared with n types of phase-shifted predetermined synchronization patterns, and when they match for each time slot, the number of matches is counted, and the counted value is n. n×r=N continuous coincidence counting means that output a coincidence pulse when the above-mentioned coincidence pulses are reached, and output a reset pulse when they do not match; and the time at which these coincidence counting means output the coincidence pulses. A frame synchronization circuit comprising: synchronization checking means for extracting a slot and using it as the frame trigger pulse.