JPH0817378B2 - Block synchronization method - Google Patents

Description

The present invention relates to block synchronization when performing frame synchronization or error correction in data transmission, and more particularly to a block synchronization method capable of shortening the block synchronization time.

(Prior Art) FIG. 4 shows a conventional block synchronization circuit. Where n
Block synchronization is performed using only the syndrome calculation result of one of the sequences. That is, when the syndrome is 1 in the asynchronous state, the frame pulse is shifted by 1 bit and the syndrome calculation is performed. As a result, if the syndrome is 1, a 1-bit shift is performed again, and this is repeated until the syndrome becomes 0.

Here, if the syndrome is 0, it is assumed that the block synchronization has been established, and the frame pulse having the same block synchronization phase is used without bit shifting.

Normally, to avoid false synchronization, for example, the syndrome is 0
The block is judged to be in synchronization (forward protection) when the block continues twice, but the number of protection steps is set to 1 here for simplicity.

(Problems to be Solved by the Invention) In order to use the above method, the maximum pull-in time T ₀₁ in the conventional circuit is given by the following equation.

T ₀₁ ≈Lx (L-1) xT (1) where L is the frame length and T is the 1-bit period.

However, T ₀₁ should be as small as possible. Similarly, regarding frame synchronization, one of the plurality of signal sequences is synchronized, and other sequences are read-synchronized.

SUMMARY OF THE INVENTION An object of the present invention is to provide a block synchronization method capable of shortening the block synchronization pull-in time in order to solve the above-mentioned problems of the conventional block synchronization circuit.

(Means for Solving the Problems) The present invention relates to (i) shifting a block initial phase for each of a plurality of sequences, calculating a syndrome from the same phase of each sequence, and (ii) a plurality of data having the same block initial phase. The most important feature is to establish block synchronization by calculating the syndrome from different phases for each column. It differs from the conventional technique in that the block synchronization pull-in time is shortened.

(Operation) In the present invention, an error correction code is targeted, and when there is no error on the receiving side (syndrome = 0), it is regarded as a synchronized state, and when there is an error (syndrome = 1), it is regarded as an asynchronous state. On the receiving side, the phase of the frame pulse is shifted by 1 bit, and when synchronization is achieved in any of the series (syndrome = 0), the predetermined series of frame pulses are supplied to other series with the series as a reference, and the whole series is supplied. Can be synchronized.

(Embodiment 1) FIG. 1 is a block diagram showing an embodiment of the invention shown in claim (1). In this figure, 256QAM or 8
The sequence is sent synchronously, and the parity bit is inserted into all eight sequences to shorten the block synchronization time. 11 to 18 are input data of 8 series, 21 to 28 are syndrome calculation circuits, and 31 to 38 are signals indicating syndromes. Reference numeral 40 denotes a first frame counter, which outputs a first frame pulse shifted by 1 bit from the previous block in a time slot equal to each series. A second frame counter 50 receives the first frame pulse and a signal indicating the syndrome of each series, and outputs eight series of second frame pulses having K bits of different initial phases. Reference numeral 60 is a frame pulse selection circuit that receives the first and second frame pulses and a signal indicating the syndrome of each series as input and selects and outputs the first or second frame pulse, and 70 is a clock signal. First, in the case of non-synchronization, the syndromes of 31 to 38 are all 1. In this case, 60 frame pulse selection circuits select the first frame pulse. Therefore, each syndrome calculation circuit calculates the syndrome with the same initial phase. When all the results are 1, the frame pulse shifted by 1 bit from the previous block output from the first frame counter 40 is input to each syndrome calculation circuit, and the repeated syndrome is calculated. Next, when the syndrome of any of the series becomes 0, the second frame counter 50
Then, a frame pulse equal to the first frame pulse at that time is output based on that sequence, and the other 7 sequences are K
The frame pulse shifted bit by bit is output. At this time, the frame pulse selection circuit of 60 selects the second frame pulse, and each syndrome calculation circuit calculates the syndrome with the initial phase shifted by K bits as in the transmitted data system, and the synchronization is established. Since block synchronization is performed with the configuration described above, the maximum pull-in time T ₀₂ is T ₀₂ ≈ {Lx (L / 8) + Lx (7/8)} xT (2), which is about 1/8 that of (1). It can be shortened.

In the above description, an example in which parity bits are inserted into all eight sequences has been described, but it is not always necessary to insert parity bits into signals of all sequences, and some sequences may have parity bits not inserted. Since signals of all series are transmitted in synchronization on the transmitting side, even a series in which no parity bit is inserted can be synchronized on the receiving side in accordance with the sequence with probability of synchronization. This is the same procedure as in the prior art.

(Embodiment 2) In the invention shown in claim (2), 8 is set on the transmitting side.
When the parity bits are inserted in the same time slots in the series data and the sequences become asynchronous, as in (1), the syndromes of all series become 1, and the frame pulse selection circuit selects the first frame pulse. It
Here, unlike the case of (1), in the first frame pulse, eight series of frame pulses shifted by 1 bit from the previous block and shifted by K bits in each series are output. Next, the syndrome is repeatedly calculated using the first frame pulse. Next, when the syndrome of any of the series becomes 0, the second frame pulse is selected. Also here, unlike the case of (1), the second frame pulse is synchronized with the frame pulse of the series at the time when the syndrome becomes zero. Therefore, after synchronization is established, the syndrome is calculated with the same time slot in each series as the initial phase, as in the transmitting side. With the configuration described above, the same effect as that of claim (1) can be obtained.

FIG. 2 shows the time relationship between the frame pulses on the transmitting side and the receiving side of the first invention. Here, the block length is 9 and 3
This is the case of transmitting a series of signals. On the transmitting side, the insertion time slot of the frame pulse is shifted by 3 bits. On the other hand, in the first block, a syndrome is calculated by inserting a frame pulse in the same time slot in each series, but the syndrome is 1 because each series is not synchronized with the frame pulse on the transmission side. Therefore, in the next block, the frame pulse is inserted into the time slot shifted by 1 bit from the previous block, and the syndrome is calculated again. By repeating this, the second stream is synchronized with the transmitting side in the third block and the syndrome becomes zero. Here, synchronization is established, and synchronization is established for all sequences after the fourth block.

FIG. 3 shows the time relationship of the frame pulse on the transmitting side and the receiving side of the second invention. On the transmission side, frame pulses are always inserted in the same time slot for each series. On the receiving side, a frame pulse is inserted into a time slot shifted by 3 bits to calculate the syndrome. When the syndrome is all series 1, the frame pulse is inserted into the time slot shifted by 1 bit in each series in the next block, and the repeated syndrome is generated. calculate. Here, synchronization is achieved in the third sequence at the third block, and block synchronization is established with the entire sequence after the next block.

In the above description, an example in which parity bits are inserted into all eight sequences has been described, but it is not always necessary to insert parity bits into signals of all sequences, and some sequences may have parity bits not inserted. Since signals of all series are transmitted in synchronization on the transmitting side, even a series in which no parity bit is inserted can be synchronized on the receiving side in accordance with the sequence with probability of synchronization. This is the same procedure as in the prior art.

(Effects of the Invention) As described above, block synchronization is established by using the syndromes of a plurality of series of data, so that the block synchronization pull-in time can be shortened. In particular, in the present invention, the syndrome calculation circuit for error correction decoding in the error correction decoders provided for each of a plurality of streams can be shared for establishing synchronization, so that the synchronization pull-in time can be shortened without increasing the circuit scale. Can be realized.

In the example shown in the embodiment, the parity bits are inserted in 8 sequences, which is shortened to about 1/8 from the equations (1) and (2).

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a time relationship of frame pulses of the first embodiment, and FIG.
FIG. 4 is a diagram showing a time chart showing the time relationship of the frame pulses of the second embodiment, and FIG. 4 is a block diagram of a conventional block synchronization system. 11 to 18 ... 8 series of input data, 21 to 28 ... syndrome calculation circuit of each series, 31 to 38 ... signal indicating syndrome, 40 ... first frame counter, 41 to 48 ... first Frame pulse, 50 ... Second frame counter, 51-
58 …… second frame pulse, 60 …… frame pulse selection circuit, 61-68 …… selected frame pulse, 70 ……
Clock signal.

Claims (2)

[Claims] 1. A block synchronization method in which signals encoded by a plurality of (n) series erroneous re-correction codes in which clock synchronization is established are transmitted in parallel, and block synchronization is established at the reception side. For the (m: m ≦ n) series signal, Ki bits (i = 1 to 1) are respectively set from the block initial phase of the series that is the reference time slot in which the parity bit is inserted.
m, Ki are arbitrary integers), and the receiving side calculates the syndromes of specific m sequences from the same initial phase. If none of the syndromes is 0, the initial phase shifted by 1 bit from the previous block is restarted. The calculation of the syndrome is repeated, and when the syndrome of any one of the sequences becomes 0, the sequence is used as a reference, and for the other (m-1) sequences, the block initial phase is set in the shifted time slot in the same manner as the transmission side. And the remaining (n−m) series of the n series are synchronized according to the block initial phase of one or a plurality of series of the m series of signals. 2. A block synchronization method in which signals encoded by a plurality (n) series of error correction codes in which clock synchronization is established are transmitted in parallel and block synchronization is established at the reception side, and a plurality of specific ( Parity bits are inserted in equal time slots for m: m ≦ n) signals, and K _i bits (i =
1-m, K _i are arbitrary integers) The syndrome is calculated with the shifted time slot as the block initial phase, and if none of the syndromes is 0, the syndrome is calculated again from the initial phase shifted by 1 bit from the previous block. If the syndrome of any one sequence becomes 0, m sequences are synchronized with the block initial phase of that sequence, and the remaining (n−m) sequences of the n sequences are m sequence signal blocks. Block synchronization method characterized by synchronizing according to the initial phase.