JPH03202910A - Synchronizing circuit - Google Patents

Abstract

PURPOSE:To synchronize an asynchronizing signal to a clock to securely output them by providing a coincidence detection circuit and detecting that the output of a first syncrhonization circuit and that of a second synchronization circuit are equal for respective bits. CONSTITUTION:The asynchronizing signal is synchronized by the clock of the first synchronization circuit 11 and it is furthermore synchronized by the second synchronization circuit 12 by the clock whose fetching timing is different from the first synchronization circuit 11. Output signals from the first and second synchronization circuits are inputted to the coincidence detection circuit 13 and it is investigated whether respective bits of plural bits are accurately fetched or not. When the output signals of the first and second synchronization circuits coincide, a third synchronization circuit 14 outputs the synchronizing signal. Since the timing of the clock for fetching the asynchronizing signal differs in the first and second synchronization circuits even if the change periods of respective bits of the asynchronizing signals slightly differ, the asynchronizing signal can accurately be shycnronized in one of the circuits.

Description

[Detailed Description of the Invention] [Summary] Regarding an asynchronous signal synchronization circuit that outputs asynchronous signals in synchronization with a clock, the present invention relates to an asynchronous signal synchronization circuit that outputs asynchronous signals in synchronization with a clock. The purpose of the synchronization circuit is to provide a synchronization circuit that requires no effort, and in a synchronization circuit that outputs an asynchronous signal in synchronization with a clock, a first synchronization circuit that latches each bit of the asynchronous signal; a second synchronization circuit that latches each bit of the asynchronous signal after a certain period of time from when the circuit latches the asynchronous signal, and all corresponding outputs of the first synchronization circuit and the second synchronization circuit; and a third synchronization circuit that latches the output signal of the first synchronization circuit or the second synchronization circuit when the coincidence detection circuit detects a match. It is configured to have the following.

[Industrial Application Field] The present invention relates to an asynchronous signal synchronization circuit that outputs an asynchronous signal in synchronization with a clock.

[Conventional technology]

In conventional synchronization circuits, when trying to capture an asynchronous signal at the rising or falling timing of the own device's clock, the asynchronous signal is "I II → "0"' or "0°" The timing of switching to
A flip-flop (hereinafter referred to as D) that captures this asynchronous signal
There are cases in which the clock capture timings of the DFFs (referred to as FFs) match (that is, the setup or hold times of the DFFs are not satisfied). At this time, the operation becomes unstable and it is uncertain whether the output level will settle to "'1" or "'0", and oscillation may occur until it settles to "'1°" or "0°". Normally, this phenomenon always occurs in an asynchronous circuit, so by installing a DFF after the output of the DFF and distributing a clock that is out of phase with the -stage DFF, the propagation of unstable levels can be prevented. Often preventable.

A circuit shown in FIG. 7 is a common circuit that outputs a 1-bit asynchronous signal in synchronization with a clock pulse. In the figure, 71-1 is the first DFF, and 71-2 is the second DFF.
It is. xl is an asynchronous signal and Y is a synchronization signal.

T I and T z are clock pulses for the first DFF 71-1 and the second DFF 71-2, respectively; the clock T1 is a pulse that rises at time T1, and the clock T2 is a pulse that rises at time T2. However, T+-I-
It is Tz. Therefore, the asynchronous signal x1 is transmitted to the first DFF7.
1-1, is output as an output signal Q1 at clock T, and enters the second DFF 71-2. This second DF
The F71-2 outputs the output signal Q2 at the clock T2.

FIG. 8 is a diagram showing a time chart of a conventional circuit (at the time of a 1-bit asynchronous signal). In the figure, from the top, the asynchronous signal XI, clock TI, clock T2, first DFF7
1-1 output Q l , second DFF 71-2 output Q
It is 2. The time chart in FIG. 8 will be explained with reference to FIG. In FIG. 7, the asynchronous human input signal Xl is output in synchronization with the rising edge of the clock T1 entering the first DFF 71-1. However, as mentioned above, the timing of change of the asynchronous signal , the level of the output waveform settles in the order of "1°" and "0". If the output signal Q is stabilized by the rising edge ■ of the clock T2, this output signal Q is synchronized by the rising edge ■ of the clock T2 of the second DFF 71-2, and a stable output signal Q2 is outputted by the rising edge ■ of the 0° clock T2. If it does not settle down by then, this output signal Q1 will be
Since this coincides with the rising edge (2) of the clock T2 of the DFF 7m-2, the output signal Q2 becomes unstable for a certain period of time as before.

Therefore, by sampling the value of the output signal Q1 by the second DFF 71-2 at the rising edge of T2 delayed by the above period or more, a stable output signal Q2 can be output [phase].

The case where the asynchronous signal x1 consists of one bit has been considered above, but a case will be explained in which -m receives the asynchronous signal X2 consisting of a plurality of bits in synchronization with the clock. Generally, when the desynchronized signal X2 is composed of a plurality of bits, the timing at which the signal changes depending on each bit is slightly different. Therefore, when the circuit shown in FIG. 7 is used, there will be a bit that coincides with the rising edge of the clock pulse T at the change timing of the asynchronous signal x2. Therefore, the synchronization signal Y1 in this case is “0
Since there is a bit that is undefined whether it will be `` or 1'', its value cannot be used.

Therefore, conventionally, multiple bits have been synchronized by using a strobe signal. FIG. 9 is an example of a circuit for synchronizing a plurality of bits of asynchronous signals using a strobe signal. In the figure, 9
1-1 to 91-3 are OFF, and the first DFF9
11 uses the strobe signal S manually and the clock pulse T
, and outputs an output signal Q in synchronization with . Second DFF
912 uses the output signal Q1 as human power, and the clock pulse T2
The output signal Q2 is output in synchronization with the output signal Q2. The third DFF uses the multi-bit asynchronous signal X2 manually and outputs the previous output signal Q
2 and outputs a synchronizing signal Y2.

Figure 1O is a time chart of the conventional circuit (when asynchronous signals with multiple focus points are used). In the figure, from the top, an asynchronous signal X2 consisting of multiple bits, a strobe signal S1, a clock pulse T
I, under clock pulse 2 They are the output signal QI of the first DFF 91-1, the output signal Q Z of the second DFF 91-2, and the output signal Y2 of the third DFF 913. asynchronous signal x
2 is a signal that comes in parallel for each bit, for example, ``rooolo'', rl, which consists of 5 pintos.

The data signals are in the form of "ioo", "rlooll", . . . . This is a case where the clock T1 and the clock Tt have 5 cycles per data of the asynchronous signal x2. First, the strobe signal S entering the first DFF 91-1 is synchronized with the clock T1, and the output signal Q1 is synchronized with the clock T1.
Output as . That is, the rise of clock T,
The output signal Q is output as @'. At this time, since the change timing of the strobe signal and the rising edge of the clock T1 coincide, the output signal Q1@' swings and becomes "1".
It ends up being ``or °'O°''.

Here, when it settles to ", 1" (solid line), the output signal Q2 is synchronized with the rising edge of the next clock T2.
O' (solid line) outputs as "1".

This output signal Q2 is input as a clock to the third DFF. Then, the rising edge of this output signal Q2 is 0'
■' which synchronizes with and outputs the asynchronous signal X2 as the output signal Y2.

On the other hand, when it settles to "0" (dotted line), the output signal Q2 ° "1" is synchronized with the rising edge of the next clock T2, instead of with the rising edge of the next clock T2.
0' (dotted line) to output as ''.

This output signal Q2 is input as a clock to the third DFF. Then, when this output signal Q2 rises, it becomes 0.
' and outputs the asynchronous signal X2 as the output signal Y2. Therefore, even if the rising edge of the clock T1 coincides with the change timing of the strobe signal S, the asynchronous signal
100. can be output.

[Problem B to be Solved by the Invention] FIG. 11 is a time chart when the asynchronous signal has multiple bits. In this case, the clock TI and the clock T2 have three cycles per asynchronous signal X2. First, the strobe signal S entering the first DFF 91-1 is synchronized with the clock T1 and output as the output signal Q1. That is, 0' is output as the output signal Q at the rising edge of the clock T1. At this time, since the change timing of the strobe signal and the rising edge of the clock T coincide, the output signal Q, @' swings and becomes either °1" or "0".
``I've settled into it.

Here, when it settles to "l'" (solid line), the output signal Q2 is synchronized with the rising edge of T2 on the next
Output as “1” @′ (solid line).

This output signal Q2 is input as a clock to the third DFF. Then, the rise of this output signal Q2 ■'
It synchronizes with and outputs the asynchronous signal
Instead, the output signal Q2 ° is output as “1” in synchronization with the rising edge of the next clock T2 [phase]’
(dotted line).

This output signal Q2 is input as a clock to the third DFF. Then, it synchronizes with the rising edge [phase]' of this output signal Q2 and outputs the asynchronous signal
At the time of [phase]′ when 2 is determined, the asynchronous signal X2 has already changed to the next data “10011”°, so the asynchronous signal
"10100" cannot be output.

In other words, the length of the cycle time of the strobe synchronization clock TI and clock T2 of the synchronization circuit that receives the strobe signal S determines whether the effective asynchronous signal x2 can be outputted in synchronization with the clock. Therefore, the clock T5 . It is necessary to consider the cycle time of clock T2.

As described above, there is a problem in that a synchronization circuit that synchronizes a plurality of bits of asynchronous signal X2 requires a strobe signal S to properly synchronize each bit. Furthermore, when outputting the asynchronous signal X2 from the output source to the reception synchronization circuit, it is necessary to match the intervals between the plurality of asynchronous signals X2 and the strobe signal S. There is a problem in that the pulse periods of the clock TI and the clock T2 must always take the asynchronous signal x2 and the strobe signal S into account.

SUMMARY OF THE INVENTION An object of the present invention is to provide a synchronization circuit that reliably outputs an asynchronous signal in synchronization with a clock, and that does not require much effort in setting clock pulses.

[Means to solve the problem]

FIG. 1 is an explanatory diagram of the principle of the present invention. In the figure, 11 is the first
This is a synchronization circuit that receives a multi-bit asynchronous signal X as input, latches each bit with a first DFF, and samples its output with a second DFF.

12 is a second synchronization circuit, which inputs a multi-bit asynchronous signal
The third latches each signal line after a certain period of time from the latching of F.
It consists of a DFF and a synchronization circuit whose output is latched by a fourth DFF.

A coincidence detection circuit 13 detects for each bit whether the output of the first synchronization circuit and the output of the second synchronization circuit are equal. The coincidence detection circuit 13 compares each bit of the first synchronization circuit 11 and the second synchronization circuit 11.

14 is a third synchronization circuit, and the coincidence detection circuit 13
The fifth DF latches the output of the first synchronization circuit or the output of the second synchronization circuit only when all bits of the first synchronization circuit and the second synchronization circuit are equal.
It is equipped with F.

[For production]

In the present invention, the asynchronous signal X is synchronized with the clock of the first synchronization circuit 11, and further synchronized with the second synchronization circuit 12 using a clock having a different acquisition timing from that of the first synchronization circuit 11. The output signals from the first and second synchronization circuits enter a coincidence detection circuit 13 to check whether each of the plurality of bits has been correctly captured. When the output signals of the first and second synchronization circuits match, the third synchronization circuit 14 outputs the synchronization signal Y.
I am trying to output .

Therefore, even if the timing of change of each bit of the asynchronous signal X is slightly different, the timing of the clock that takes in the asynchronous signal The asynchronous signal X can be accurately synchronized.

〔Example〕

FIG. 2 shows an embodiment of the invention. In the figure, 11 is the first
This is a synchronization circuit that uses a 32-bit asynchronous signal The second DFF 2i2 outputs an output signal Q2.

12 is a second synchronization circuit, which inputs the third 0FF21-3 which uses the 32-bit asynchronous signal X and outputs the output signal Q in synchronization with the clock pulse T1, and the previous output signal Q. It consists of a fourth DFF 21-4 that outputs an output signal Q4 in synchronization with the clock pulse T2.

A coincidence detection circuit 13 includes a comparator 22 and an AND gate 23 that performs an AND operation between the output signal C3 of the comparator 22 and the clock T.

FIG. 3 is a block diagram of one embodiment of this coincidence detection circuit 13, which is composed of EXNORs 31-1 to 31-32 and AND32. Output signal Q corresponding to each bit of output signal Q2
Bit 4 is the human power of EXNOR31-1 to 3m-32. Therefore, EXNor? only when each corresponding bit matches. outputs the logic rlJ. Therefore, only when all 32 bits match, comparator 1
3, the logic flJ is output as the output signal C1.

14 is a third synchronization circuit, and a fifth DFF 21-5
Consisting of This fifth DFF 21-5 receives the output signal Q of the first synchronization circuit 11, and the output signal C9 of the comparator 22 and the clock T.

It is synchronized with the clock pulse obtained by AND23.

FIG. 4 is a timing diagram of the clock. In the figure, clocks T0 to T3 sample data at rising edges at times T0 to T, respectively.

FIG. 5 is a time chart of an embodiment of the present invention, and is an example when the data change of the asynchronous signal does not coincide with the rising edge of the clock pulse.

In the figure, from the top, the asynchronous signal X, the first DFF21-
Output signal Q1 of (2), output signal Q of second DFF21-2
! , the output signal Q3 of the third DFF21-3, and the fourth DF
F214 output signal Q4, comparator 22 output signal C1, fifth DFF21-5 write clock signal,
This is the output signal Y of the fifth DFF 25-1.

The explanation will be given below with reference to FIG.

First, consider the case where a 32-bit human-powered asynchronous signal X enters the first synchronization circuit 11. The input asynchronous signal X is the clock T of the first DFF2m-1 of the first synchronization circuit. Output signal Q1 is output in synchronization with the rising edge of (1)
. In this case, the data switching timing and the clock T0 capture timing do not match, so the output signal Q is determined. This output signal Q, is the second D
It is taken into the FF 21-2 and outputted as an output signal Q2 in synchronization with the clock T2 (2). This output signal Q2 is fixed because it incorporates the fixed output signal Q1. Next, the human-powered asynchronous signal X is sent to the second synchronization circuit 1.
Let's consider the case where it falls into 2. The input asynchronous signal X is outputted as an output signal Q3 in synchronization with the rising edge of the clock T of the third DFF 21-3 of the second synchronization circuit (3). In this case as well, the data switching timing and the clock T capture timing do not match, so the output signal Q3 is determined. Therefore, the output signal Q4 is also determined as described above (4).

Then, the output signal Q2 of the first synchronization circuit 11 and the output signal Q4 of the second synchronization circuit 12 enter the coincidence detection circuit 13. By the way, since the previous output signals Q1 and Q2 have been determined, the logic r that the output signals CI match is established.
lJ enters (5). Therefore, the input signal Q2 to the fifth DFF 215 is output as the synchronization signal Y (7) in synchronization with the rising edge of the clock T (6).

FIG. 6 is a time chart of the embodiment of the present invention, and is an example when the data change of the asynchronous signal coincides with the rising edge of the clock pulse.

First, consider the case where a 32-bit human-powered asynchronous signal X enters the first synchronization circuit 11. The input asynchronous signal
An output signal Q is output in synchronization with the rising edge of the clock T0 of the first DFF 211 of the synchronization circuit (1).
'. In this case, since the data switching timing and the clock T0 capture timing match,
The output signal Q becomes undefined and undetermined. In other words, “0゛°
After touching ``1pa'', it stabilizes to one side. Therefore, some of the 32 bits may match by chance. This uncertain signal Q2 is synchronized with the clock T of the second DFF 21-2 and is output as an output signal Q2 (2)'. At this time, the output is stable but not accurate. Next, considering the case where the 32-bit input asynchronous signal X enters the second synchronization circuit 12, the zero human input asynchronous signal X is:
Clock T of the third DFF21-3 of the second synchronization circuit
An output signal Q is output in synchronization with the rising edge of + (3)'. In this case, the data switching timing and the clock TI capture timing do not match, so the output signal Q1 is determined. For this reason, the fourth DF
The determined output signal Q4 is output from F21-4 (
4)' Output signals Q2 and Q4 are input manually to the coincidence detection circuit 13. Since all the bits do not match in this match detection circuit 13, logic "0" is detected from any EXNOR circuit.
1 is output. If any one of them has logic rQJ,
The output signal CI of the AND circuit becomes logic rQJ (5)'
Therefore, the fifth DF which is ANDed with the clock T,
F21-5 maintains the previous output (6)' On the other hand, in the first DFF 211 of the first synchronization circuit, the next clock T does not match the rising timing of the data signal. Therefore, since the determined value can be output in synchronization with the clock T1, the output signal Q becomes a determined signal (7
)'The output signal Q2 outputted in synchronization with the clock T2 is determined (8)'. In addition, the second synchronization circuit also outputs the determined output signals Q, ,Q, (9
)', 00)'. Therefore, the coincidence detection circuit 13 outputs the output signal C3 of logic rlJ, so 01)
', an output signal that is 02) M+I constant is output in synchronization with the clock T303)' [Effect of the Invention] As explained above, according to the present invention, the strobe signal and the Do not use strobe synchronization clock. Therefore, there is no need to consider the cycle time of the strobe synchronization clock with respect to the asynchronous signal to be captured. Furthermore, even if the signal change timing of the asynchronous signal and the rising timing of the clock match, a valid asynchronous signal can be reliably output as an output signal.

Therefore, the asynchronous signal can be reliably output in synchronization with the clock.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a block diagram showing an embodiment of the invention, Fig. 3 is a configuration diagram of an embodiment of a coincidence detection circuit, Fig. 4 is a clock timing diagram, and Fig. 5 is a block diagram showing an embodiment of the invention. Figure 6 is a time chart diagram of an embodiment of the present invention (when the rise of the asynchronous signal does not match), Figure 6 is a time chart diagram of an embodiment of the present invention (when it coincides with the rise of the asynchronous signal), Figure 7 The figure shows the synchronization circuit for 1 bit, Figure 8 shows the time chart (for 1 bit), Figure 9 shows the synchronization circuit for multiple bits, and Figure 1O shows the time chart (
(when multiple bits)...Clock 5 cycle time Figure 11 is a time chart (when multiple bits)...
・It is clock 5 cycle time. In the figure, ll: first synchronization circuit 12: second synchronization circuit 13, coincidence detection circuit 14: third synchronization circuit.

Claims (1)

[Claims] 1) In a synchronization circuit that outputs an asynchronous signal in synchronization with a clock, a first synchronization circuit that latches each bit of the asynchronous signal (
11), a second synchronization circuit (12) that latches each bit of the asynchronous signal after a certain period of time from when the first synchronization circuit (11) latches the asynchronous signal, and a first synchronization circuit. (1
a coincidence detection circuit (1) that detects that all corresponding bits of the output of the second synchronization circuit (12) are equal;
13) and a third synchronization circuit that latches the output signal of the first synchronization circuit (11) or the second synchronization circuit (12) when a match is detected by the match detection circuit (13). (
14) A synchronization circuit comprising: 2) The first synchronization circuit (11) latches each bit of the asynchronous signal with the first DFF, and
A second DFF (11-2) that latches the output of the first DFF bit by bit after a certain period of time from the latch of 1-1).
The second synchronization circuit (12) includes a third DFF (12-1) that latches each bit of the asynchronous signal after a certain period of time by the latch of the first DFF, and a third DFF.
After a certain period of time from the latch of FF (12-1), the third DF
The fourth latches the output of F(12-1) for each bit.
A synchronization circuit comprising a DFF (12-2).