JP2004012279A - Pulse interval measurement circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a measurement circuit wherein pulse intervals can be measured without using a synchronous circuit of start clock of high precision even when interval is short. <P>SOLUTION: The pulse interval measurement circuit is provided with a clock circuit 5; D-F/Fs 1, 2 for a first stage pulse and a next stage pulse which converts first stage pulse input and next stage pulse input into a first stage logic signal and a next stage logic signal; a counter 7 which counts clock number when the first stage logic signal, the next stage logic signal and a clock signal are logic H; pulse delay circuits 10, 11 for the first stage pulse and the next stage pulse which delay the first stage logic signal and the next stage logic signal by a delay amount wherein period of the clock signal is divided equally; D-F/Fs 16, 17 for latching the first stage logic signal and the next stage logic signal which latch the first stage logic signal and the next stage logic signal which are delayed; an adder 24 which adds a counted value of the counter to an output of the first stage logic signal latch; and a subtracter 25 which calculates pulse interval by subtracting an output of the next stage logic signal latch from an output of the adder. As a result, pulse interval can be measured with high precision by a period equal to or smaller than the period of the clock signal. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a pulse interval measuring circuit of a radiation measuring apparatus that measures a radiation incident position by obtaining a time difference between both ends of an optical fiber of a pulse signal generated when radiation enters the optical fiber.
[0002]
[Prior art]
A conventional pulse interval measuring circuit will be described with reference to the drawings. FIG. 13 and FIG. 14 are a diagram showing a configuration of a conventional pulse interval measuring circuit disclosed in, for example, Japanese Patent Application Laid-Open No. H4-244971, and a timing chart showing its operation.
[0003]
In FIG. 13, reference numeral 91 denotes a timing controller; 92, an inverter for inverting a start pulse enable, preset (PRST), and reset (RST) signals of the timing controller 91; 93, a preset signal is generated by input of a measured pulse and start pulse enable. AND gate 94, counter for counting up the pulse interval to be measured by clock (CK) input, 95 for initial value generator for setting initial value of counter 94, 96, 98, 910, 912 for clock (CK) and delay Phase memory circuits 97, 99, and 911 for detecting the phase of the measured pulse are delay elements for sequentially delaying the clock (CK) cycle T by a delay increment that is equally divided.
[0004]
In the same figure, 913 is a first register for storing the count value of the counter 94, 914, 915, 916 are E-OR gates for detecting a change point of a logical output value between two adjacent phase memory circuits, Reference numeral 917 denotes a three-input NOR gate for processing when a change point of the logical output value cannot be detected, 918 denotes a fixed value generator for generating a delay time corresponding to the change point, and 919 denotes a count value and a fixed value of the register 913. The adder 920 adds the delay time of the generator 918, the strobe generator 920 is activated by the pulse to be measured most delayed and generates a strobe signal (STB), and the reference numeral 921 indicates the added value of the adder 919 by the strobe signal (STB). A second register 922 for latching generates a reset signal (RST) for the phase memory circuits 96, 98, 910, 912. A gate.
[0005]
Further, in the figure, reference numerals 961, 981, 9101, and 9121 denote AND gates for inputting the measured pulse input to the phase memory circuit by the start pulse enable, preset (PRST), and reset (RST) signals of the timing controller 91, and 962, 982. , 9102, and 9122 are RS-F / Fs that latch the pulse to be measured, and 963, 983, 9103, and 9123 are DF / Fs that latch the outputs of the RS-F / Fs 962, 982, 9102, and 9122.
[0006]
Next, the operation of the conventional pulse interval measuring circuit will be described with reference to the drawings.
[0007]
A start pulse enable signal, a preset signal (PRST), and a reset signal (RST) are output from the timing controller 91 via the OR gate 922, and the RS-F / Fs 962, 982, and 982 in each of the phase memory circuits 96, 98, 910, and 912 are output. 9102, 9122 and DF / Fs 963, 983, 9103, 9123 are reset, and the binary counter 94 is activated by an enable signal (ENB) given from the timing controller 91.
[0008]
Next, when a start pulse P0, which is the first pulse, is supplied from the pulse input terminal to be measured, a preset signal (PRST) is supplied through an AND gate 93, thereby loading -1 from the initial value generator 95, The count-up is started from −1 by the clock (CK) from the timing controller 91.
[0009]
In this case, the AND gates 961, 981, 9101, and 9121 are closed by the above-described start pulse enable, preset signal (PRST), and reset signal (RST), so that the start pulse P0 is RS-F / F962, 982, 9102 and 9122 are not transmitted.
[0010]
Next, when the first pulse P1 from the start pulse P0 is applied to the pulse input terminal to be measured, the AND gate 961 outputs P1 as it is, and the AND gates 981, 9101, and 9121 respectively provide the delay element 97 (T / 4), 99 (2T / 4), and 911 (3T / 4), delay outputs are sequentially input to RS-F / F 962, 982, 9102, 9122, and these RS-F / F 962, 982, 9102, 9122 is set.
[0011]
Next, the outputs of the RS-F / Fs 962, 982, 9102, 9122 are latched by the corresponding DF / Fs 963, 983, 9103, 9123 at the timing of the clock (CK).
[0012]
The counter 94 and the register 913 are composed of m bits, and the count value of the counter 94 when an output pulse is given from the AND gate 9121 is latched in the register 913.
[0013]
FIG. 14 illustrates a case where a true count value is Nk and the timing pulse Pl is Nk + 5/8.
[0014]
In this example, the output of the AND gate 961 is generated at the count value Nk-1 of the counter 94. Since the outputs of the AND gates 981, 9101, and 9121 are delayed from the output of the AND gate 961 by 1/4, 2/4, and 3/4, respectively, the count value of the register 913 is Nk.
[0015]
The timing of the pulse Pl is measured with a resolution of 1/4 of the LSB of m bits, that is, with m + 2 bits, and the arithmetic processing at that time is performed as follows.
[0016]
Since the logical outputs of the DF / Fs 963 and 983 are 1 and the logical outputs of the DF / Fs 9103 and 9123 are 0, the logical output 1 of the E-OR gates 914, 915, and 916 is generated. Is only the E-OR gate 915.
[0017]
As described above, either one of the E-OR gates 914, 915, and 916 generates an output, or does not generate an output depending on the timing of the pulse Pl.
[0018]
When the logical output 1 is output from the E-OR gates 914, 915, and 916, the fixed value generator 918 converts the fixed values of 3/4, 2/4, and 1/4 corresponding to the shift into binary 2 bits. It is transmitted as an output, and when it is not output from each of the E-OR gates 914, 915, and 916, a fixed value of 1 is represented by binary 2 bits and output by a NOR gate 917.
[0019]
Therefore, the fixed value generator 918 outputs a binary 2-bit value representing ／. The adder 919 adds the output value of the register 913 and the output value of the fixed value generator 918, and outputs an addition result. The strobe generator 920 generates a strobe signal (STB) in response to the output pulse signal of the AND gate 9121, and the register 921 latches the output value of the adder 919 when receiving this signal and outputs it with m + 2 bits.
[0020]
When the strobe signal (STB) is generated, the register 913 and the phase memories 96, 98, 910, 912 are reset. Since the output value of the register 913 is a binary Nk and the output value of the fixed value generator 918 is a binary 2 bit value of 2/4, the output of the register 921 is 1/4 corresponding to (Nk + 2/4). It is a binary m + 2 bit value to be LSB.
[0021]
[Problems to be solved by the invention]
In the conventional pulse interval measuring circuit as described above, the start clock must be synchronized by the pulse input P0, a high-precision synchronous circuit is required, and the configuration is required when measuring the pulse interval of continuous pulses. There was a problem that it became complicated.
[0022]
In addition, when the pulse interval is shortened, there is a problem that the delay time of each component is greatly affected by the large number of component configurations.
[0023]
SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and a pulse interval between consecutive pulses can be easily configured without a synchronization circuit for a start clock by a pulse input P0, and measurement is performed even when the pulse interval is short. It is an object of the present invention to obtain a pulse interval measuring circuit capable of performing the above.
[0024]
[Means for Solving the Problems]
A pulse interval measuring circuit according to the present invention includes a clock circuit for generating a clock signal, a DF / F for initial pulse for converting an initial pulse input into an initial logic signal, and a next circuit for converting a next pulse input into a next logic signal. When the pulse DF / F, the initial logic signal, the next logic signal when there is no next pulse input, and the clock signal is logic H, the number of clocks of the clock signal is counted, and the next pulse input is performed. When there is a counter, the counter for stopping the counting, the DF / F for initial logic for synchronizing the initial logic signal with the clock signal, and the D for next logic for synchronizing the next logic signal with the clock signal. F / F and the synchronized initial logic signal are sequentially delayed by a delay equal to the period of the clock signal. An initial pulse delay circuit, a next pulse delay circuit for sequentially delaying the synchronized next logic signal by a delay obtained by equally dividing the cycle of the clock signal, and an initial logic signal latch for latching the delayed initial logic signal DF / F, a next logic signal latching DF / F that latches the delayed next logic signal, and the count value of the counter and the output of the initial logic signal latching DF / F. An adder; and a subtractor for subtracting an output of the next logic signal latch DF / F from an output of the adder to calculate a pulse interval between the initial and next pulse inputs.
[0025]
In the pulse interval measuring circuit according to the present invention, the DF / F for the initial pulse and the DF / F for the next pulse are cascaded.
[0026]
The pulse interval measurement circuit according to the present invention includes a clock circuit for generating a clock signal, an initial pulse DF / F for converting an initial pulse input into an initial logic signal, and a next pulse input being converted into a next logic signal. DF / F for the next pulse to be converted, DF / F for the third pulse for converting a third pulse input into a third logic signal, the initial logic signal, and the next logic in the absence of the next pulse input A first counter that counts the number of clocks of the clock signal when the signal and the clock signal are at logic H, and stops counting when the next pulse is input; The third logic signal when there is no pulse input, and counting the number of clocks of the clock signal when the clock signal is logic H, A second counter for stopping the counting when there is a pulse input, a DF / F for initial logic for synchronizing the initial logic signal with the clock signal, and synchronizing the next logic signal with the clock signal. The next logic DF / F to be synchronized, the third logic DF / F for synchronizing the third logic signal with the clock signal, and the synchronized initial logic signal are equally divided into periods of the clock signal. An initial pulse delay circuit for sequentially delaying the synchronized next logic signal, a next pulse delay circuit for sequentially delaying the synchronized next logic signal by a delay obtained by equally dividing the cycle of the clock signal, and the synchronized third logic signal. A third pulse delay circuit for sequentially delaying the clock signal by an equal delay, and latching the delayed initial logic signal D / F for latching the next logic signal, D / F for latching the next logic signal that latches the delayed next logic signal, and D for latching the third logic signal that latches the delayed third logic signal -F / F, the count value of the first counter, and the output of the initial logic signal latch DF / F, and the output of the next logic signal latch DF / F is calculated from the added value. An adder / subtractor for calculating the pulse interval of the initial and next pulse input by subtracting the adder, an adder for adding the count value of the second counter and the output of the next logic signal latch DF / F, and the adder And a subtractor for subtracting the output of the third logic signal latch DF / F from the output of the second logic signal to calculate the pulse interval of the next and third pulse inputs.
[0027]
In the pulse interval measuring circuit according to the present invention, the delay circuit for the next pulse may be omitted, and the delay circuit for the initial pulse may be obtained by dividing the synchronized initial and next logic signals by a delay obtained by equally dividing the cycle of the clock signal. And the next logic signal latch DF / F is deleted, the initial logic signal latch DF / F latches the delayed initial and next logic signals, and the adder The count value of the counter is added to the latched initial logic signal, and the subtracter subtracts the latched next logic signal from the output of the adder to calculate a pulse interval of the initial and next pulse inputs. , The delay circuit for the initial pulse and the delay circuit for the next pulse are shared.
[0028]
Further, the pulse interval measurement circuit according to the present invention counts the number of clocks of the clock signal when the initial logic signal, the next logic signal in the absence of the next pulse input, and the delayed clock signal is logic H, The apparatus further includes a second counter that stops the counting when the next pulse input is present, and a comparison circuit that outputs an error when the count values of the counter and the second counter are indeterminate. Things.
[0029]
Further, the pulse interval measuring circuit according to the present invention is characterized in that the initial logic signal, the next logic signal in the absence of the next pulse input, and the clock of the clock signal when the clock signal delayed by the first time is logic H A second counter that counts the number and stops the counting if the next pulse input is present, the initial logic signal, the next logic signal without the next pulse input, and the second time When the delayed clock signal is logic H, the number of clocks of the clock signal is counted, and when the next pulse is input, a third counter that stops the counting is provided. The count value of the counter, the second counter, or the third counter is determined based on a predetermined condition of the output of the F / F. Further comprising a comparison circuit for outputting to the adder Zureka, said adder is for adding the outputs of said initial logic signal latch D-F / F of the comparator circuit.
[0030]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiment 1 FIG.
First Embodiment A pulse interval measuring circuit according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a configuration of a pulse interval measuring circuit according to Embodiment 1 of the present invention. In the drawings, the same reference numerals indicate the same or corresponding parts.
[0031]
In FIG. 1, 1 and 2 are DF / Fs for converting a pulse input signal into a logic input signal, 3 and 4 are delay circuits for taking timing with a clock signal, 5 is a clock circuit for generating a clock signal, and 6 Is an AND gate for a logic input signal and a clock signal, 7 is a counter for counting the number of clocks, and 8 and 9 are DF / Fs for synchronizing the logic input signal with the clock signal.
[0032]
Also, in the figure, 10 and 11 are T / 4 delay circuits of the clock signal period T, 12 and 13 are 2T / 4 delay circuits of the clock signal period T, and 14 and 15 are 3T / 3 of the clock signal period T. Four delay circuits, 16 to 23, are DF / Fs for latching delayed logic signals.
[0033]
Further, in the figure, reference numeral 24 denotes an adder for adding the count value of the counter 7 to the outputs of the delay logic signal latch circuits 16, 18, 20 and 22; , 21 and 23, a reset circuit for releasing the latch by the operation completion signal of the subtractor 25.
[0034]
Next, the operation of the pulse interval measuring circuit according to the first embodiment will be described with reference to the drawings.
[0035]
FIG. 2 is a timing chart showing an operation of the pulse interval measuring circuit according to the first embodiment of the present invention.
[0036]
When the measuring circuit is started, a reset signal is sent from the reset circuit 26 to reset all the latches.
[0037]
The pulse interval is measured by measuring the interval between the measured pulse input terminal 1 and the measured pulse input terminal 2.
[0038]
When the pulse input P0 is input to the measured pulse input terminal 1, the logic output L0 outputs a logic H signal by the logic signal conversion DF / F1. The logic output L0 is input to the AND gate 6 via the delay circuit 3, and the counter 7 counts the number of clocks under the conditions of a logic H of the logic output L0, a logic H without the input of the pulse input Pl, and a logic H of the clock signal. Count with.
[0039]
The output of the delay circuit 3 is passed through a DF / F 16 for latching a logic signal, a DF / F 18 for latching a logic signal via a T / 4 delay circuit 10, and a D / F for a logic signal latch via a 2T / 4 delay circuit 12. -F / F20, and further transmitted to the logic signal latching DF / F22 through the 3T / 4 delay circuit 14.
[0040]
The logic signal latch condition is such that when the logic output L0 is logic H and the clock signal is logic H, the logic signal latch DF / Fs 16, 18, 20, and 22 are latched.
[0041]
When the pulse input P1 is input to the measured pulse input terminal 2, the logic output L1 outputs a logic H signal by the logic signal conversion DF / F2.
[0042]
The logic output L1 passes through the delay circuit 4, passes through the logic signal latching DF / F17, passes through the T / 4 delay circuit 11, passes through the logic signal latching DF / F19, passes through the 2T / 4 delay circuit 13, and passes through the logic signal latch. The DF / F 21 is sent to the logic DF / F 23 via the DF / F 21 and the 3T / 4 delay circuit 15.
[0043]
The logic signal latch condition is that when the logic output L1 is logic H and the clock signal is logic H, the logic signal latching DF / Fs 17, 19, 21 and 23 are latched.
[0044]
The clock signal of the clock circuit 5 is used not only for counting by the counter 7 but also for measuring the delay time between the input pulse and the clock signal.
[0045]
When the pulse input P0 signal is input while the pulse input P1 signal is not input, the logic L0 signal becomes logic H, and the logic L0 signal passes through the delay circuits 10, 12, and 14, and the logic signal latch D-F / F18, 20, 22 and latches the latch DF / Fs 16, 18, 20, 22 under the condition of logic H of the first clock signal after the pulse input P0 signal is input, and furthermore, the counter 7 The count is set to 1.
[0046]
In the logic H of the next clock signal, the pulse input Pl has not been input, and the counter 7 counts up to 2. When the pulse input P1 signal is input and the logic L1 becomes a logic H, the AND gate 6 of the counter input is closed, the counting of the counter 7 is stopped, and at the same time, the logic L1 signal is passed through the delay circuits 11, 13, 15 to the logic L. The signals become logic H sequentially.
[0047]
Further, in the logic H of the next clock signal, the pulse input Pl signal is input and the logic L1 is in the logic H, so that the latch DF / Fs 17, 19, 21, and 23 are latched.
[0048]
In the example of the timing chart, the latch result of the logic signal indicates that the logic L0 signal, the T / 4 delay signal, the 2T / 4 delay signal, and the 3T / 4 delay signal are all latched by the logic H in the circuit on the pulse input P0 side. In the circuit on the input Pl side, the logic L1 signal and the T / 4 delay signal are logic H, the 2T / 4 delay signal is logic L, and the 3T / 4 delay signal is logic L.
[0049]
Further, the count value of the counter 7 is 2. The pulse interval is obtained by adding and subtracting the period T of the clock signal and the logic of the latch circuit.
[0050]
That is, all the latches on the pulse input P0 side are at logic H, which means that 3T / 4 time has elapsed.
[0051]
On the other hand, the pulse input P1 indicates that the 2T / 4 delay signal and the 3T / 4 delay signal are at logic L, and that T / 4 time has elapsed. These latch results are for correcting the count value of the counter 7, and the adder 24 obtains a result of 2T + 3T / 4 from the count value 2 of the counter 7 and the latch result on the pulse input P0 side.
[0052]
Next, a result of 2T + 3T / 4−T / 4, that is, 2T + 2T / 4 = 2.5T is obtained from the result of the adder 24 and the latch result on the pulse input P1 side by the subtracter 25.
[0053]
As described above, the delay circuit that divides the pulse interval between the pulse input P0 signal of the pulse input terminal 1 to be measured and the pulse input P1 signal of the pulse input terminal 2 to be measured by T / n by less than the clock period T is used. This makes it possible to measure accurately with a cycle shorter than the clock cycle T.
[0054]
Even if delay lines, programmable delay lines, logic ICs, print patterns, and the like are configured as delay circuits, and CMOS, ECL, FPGA, and the like are configured as other component circuit devices, measurement can be performed with high accuracy.
[0055]
Embodiment 2 FIG.
Second Embodiment A pulse interval measuring circuit according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a diagram showing a configuration of a pulse interval measuring circuit according to Embodiment 2 of the present invention.
[0056]
In FIG. 3, reference numerals 1 and 2 denote DF / Fs for converting a pulse input signal into a logic input signal, reference numerals 3 and 4 denote delay circuits for taking timing with a clock signal, reference numeral 5 denotes a clock circuit for generating a clock signal, and reference numeral 6 denotes a clock circuit. Is an AND gate for a logic input signal and a clock signal, 7 is a counter for counting the number of clocks, and 8 and 9 are DF / Fs for synchronizing the logic signal input with the clock signal. The DF / Fs 1 and 2 are cascaded as shown in FIG.
[0057]
Also, in the figure, reference numerals 10 and 11 denote T / 4 delay circuits having a clock signal period T, 12 and 13 denote 2T / 4 delay circuits having a clock signal period T, and 14 and 15 denote 3T / 3T clock signal periods T. 4 delay circuits, 16 to 23 are DF / Fs for latching delayed logic signals
[0058]
Further, in the figure, reference numeral 24 denotes an adder for adding the count value of the counter 7 to the output of the delay logic signal latch circuits 16, 18, 20, and 22, and 25 denotes a delay logic signal latch circuit 17, 19 from the output of the adder 24. , 21, and 23 are reset circuits for resetting the latch by the operation completion signal of the subtractor 25.
[0059]
Next, the operation of the pulse interval measuring circuit according to the second embodiment will be described with reference to the drawings.
[0060]
FIG. 4 is a timing chart showing the operation of the pulse interval measuring circuit according to Embodiment 2 of the present invention.
[0061]
When the measuring circuit is started, a reset signal is sent from the reset circuit 26 to reset all the latches.
[0062]
By the reset, the pulse input DF / F1 is in a state where logic H conversion is possible, and the DF / F2 is in a state where logic H conversion is stopped.
[0063]
When the first pulse input P0 is input to the pulse input terminal to be measured, the logic output L0 outputs a logic H signal by the logic signal conversion DF / F1, and the pulse input DF / F2 changes to the logic H. It will be in a convertible state.
[0064]
The logic output L0 is input to the AND gate 6 via the delay circuit 3, and counts the number of clocks under the conditions of a logic H of the logic output L0, a logic H without the input of the pulse input P1, and a logic H of the clock signal. Count at 7.
[0065]
The output of the delay circuit 3 is passed through a DF / F 16 for latching a logic signal, a DF / F 18 for latching a logic signal via a T / 4 delay circuit 10, and a D / F for a logic signal latch via a 2T / 4 delay circuit 12. -F / F20, and further transmitted to the logic signal latching DF / F22 through the 3T / 4 delay circuit 14.
[0066]
The logic signal latch condition is that when the logic output L0 is logic H and the clock signal is logic H, the logic signal latch DF / Fs 16, 18, 20, and 22 are latched.
[0067]
Next, when the pulse input Pl is input to the pulse input terminal to be measured, the logic output L1 outputs a logic H signal by the logic signal conversion DF / F2.
[0068]
The logic output L1 passes through the delay circuit 4, passes through the logic signal latching DF / F17, passes through the T / 4 delay circuit 11, passes through the logic signal latching DF / F19, passes through the 2T / 4 delay circuit 13, and passes through the logic signal latch. The DF / F 21 is sent to the logic DF / F 23 via the DF / F 21 and the 3T / 4 delay circuit 15.
[0069]
The logic signal latch condition is that when the logic output L1 is logic H and the clock signal is logic H, the logic signal latch DF / Fs 17, 19, 21, and 23 are latched.
[0070]
The clock signal of the clock circuit 5 is used not only for counting by the counter 7 but also for measuring the delay time of the input pulse with respect to the clock signal.
[0071]
When the pulse input P0 signal is input while the pulse input P1 signal is not input, the logic L0 signal becomes logic H, and the logic L0 signal passes through the delay circuits 10, 12, and 14, and the logic signal latch D-F / F18, 20, 22 and latches the latch DF / Fs 16, 18, 20, 22 under the condition of logic H of the first clock signal after the pulse input P0 signal is input, and furthermore, the counter 7 The count is set to 1.
[0072]
In the logic H of the next clock signal, the pulse input Pl has not been input, and the counter 7 counts up to 2.
[0073]
When the pulse input P1 signal is input and the logic L1 becomes a logic H, the AND gate 6 of the counter input is closed, the counting of the counter 7 is stopped, and at the same time, the logic L1 signal is passed through the delay circuits 11, 13, 15 to the logic L. The signals become logic H sequentially.
[0074]
Further, in the logic H of the next clock signal, the pulse input Pl signal is input and the logic L1 is in the logic H, so that the latch DF / Fs 17, 19, 21, and 23 are latched.
[0075]
In the example of the timing chart, the latch result of the logic signal indicates that the logic L0 signal, the T / 4 delay signal, the 2T / 4 delay signal, and the 3T / 4 delay signal are all latched by the logic H in the circuit on the pulse input P0 side. In the circuit on the input Pl side, the logic L1 signal and the T / 4 delay signal are logic H, the 2T / 4 delay signal is logic L, and the 3T / 4 delay signal is logic L.
[0076]
Further, the count value of the counter 7 is 2.
[0077]
The pulse interval is obtained by adding and subtracting the period T of the clock signal and the logic of the latch circuit.
[0078]
That is, all the latches on the pulse input P0 side are at logic H, which means that 3T / 4 time has elapsed.
[0079]
On the other hand, the pulse input P1 indicates that the 2T / 4 delay signal and the 3T / 4 delay signal are at logic L, and that T / 4 time has elapsed.
[0080]
These latch results are for correcting the count value of the counter 7, and the adder 24 obtains 2T + 3T / 4 from the count 2 of the counter 7 and the latch result on the pulse input P0 side.
[0081]
Next, a result of 2T + 3T / 4-T / 4, that is, 2T + 2T / 4 = 2.5T is obtained from the result of the adder 24 and the latch result on the pulse input P1 side by the subtractor 25.
[0082]
As described above, by using the delay circuit that divides the pulse interval between the first pulse input P0 signal and the next pulse input P1 signal of the measured pulse input terminal by T / n, the clock cycle T or less, the clock cycle T or less is used. This has the effect of being able to measure accurately with a period of
[0083]
Even if delay lines, programmable delay lines, logic ICs, print patterns, and the like are configured as delay circuits, and CMOS, ECL, FPGA, and the like are configured as other component circuit devices, measurement can be performed with high accuracy.
[0084]
Embodiment 3 FIG.
Third Embodiment A pulse interval measuring circuit according to a third embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a diagram showing a configuration of a pulse interval measuring circuit according to Embodiment 3 of the present invention.
[0085]
In FIG. 5, reference numerals 1, 2, and 31 denote DF / Fs for converting a pulse input signal into a logic input signal, reference numerals 3, 4, and 32 denote delay circuits for taking timing with a clock signal, and reference numeral 5 denotes a clock signal. Clock circuits, 6 and 27, AND gates for logic input signals and clock signals, 7, 28, counters for counting the number of clocks, 8, 9, 33, DF / Fs for synchronizing logic signal inputs with clock signals It is. The DF / Fs 1, 2, and 31 are cascaded as shown in FIG.
[0086]
In the same figure, 10, 11, and 34 are T / 4 delay circuits with a clock signal period T, 12, 13, and 35 are 2T / 4 delay circuits with a clock signal period T, and 14, 15, and 36 are clock signal 3T / 4 delay circuits having a period T, 16 to 23, and 37 to 40 are DF / Fs for latching delayed logic signals.
[0087]
Further, in the figure, reference numeral 26 denotes a reset circuit for releasing the latch by the operation completion signal of the subtracter 41, and 29 denotes an addition of the count value of the counter 7 and the delay logic signal latch circuits 16, 18, 20, 22 and a delay signal latch circuit. Adder / subtracter for subtracting 17, 19, 21 and 23; 30 is an adder for adding the count value of the counter 28 to the delay logic signal latch circuits 17, 19, 21 and 23; 41 is a delay logic signal from the adder 30 This is a subtractor for subtracting the latch circuits 37, 38, 39, and 40.
[0088]
Next, the operation of the pulse interval measuring circuit according to the third embodiment will be described with reference to the drawings.
[0089]
FIG. 6 is a timing chart showing the operation of the pulse interval measuring circuit according to Embodiment 3 of the present invention.
[0090]
When the measuring circuit is started, a reset signal is sent from the reset circuit 26 to reset all the latches.
[0091]
By the reset, the pulse input DF / F1 is in a state where logic H conversion is possible, and the DF / F2 is in a state where logic H conversion is stopped.
[0092]
When the first pulse input P0 is input to the pulse input terminal to be measured, a logic H signal is output from the logic output L0 by the logic signal conversion DF / F1, and the pulse input DF / F2 is converted to the logic H. It becomes possible.
[0093]
The logic output L0 is input to the AND gate 6 via the delay circuit 3, and counts the number of clocks under the conditions of a logic H of the logic output L0, a logic H without the input of the pulse input Pl, and a logic H of the clock signal. Count at 7.
[0094]
The output of the delay circuit 3 is passed through a DF / F 16 for latching a logic signal, a DF / F 18 for latching a logic signal via a T / 4 delay circuit 10, and a D / F for a logic signal latch via a 2T / 4 delay circuit 12. -F / F20, and further transmitted to the logic signal latching DF / F22 through the 3T / 4 delay circuit 14.
[0095]
The logic signal latch condition is that when the logic output L0 is logic H and the clock signal is logic H, the logic signal latch DF / Fs 16, 18, 20, and 22 are latched.
[0096]
Next, when the pulse input Pl is input to the pulse input terminal to be measured, a logic H signal is output from the logic output L1 by the logic signal conversion DF / F2.
[0097]
The logic output L1 passes through the delay circuit 4, passes through the logic signal latching DF / F17, passes through the T / 4 delay circuit 11, passes through the logic signal latching DF / F19, passes through the 2T / 4 delay circuit 13, and passes through the logic signal latch. The DF / F 21 is sent to the logic DF / F 23 via the DF / F 21 and the 3T / 4 delay circuit 15.
[0098]
The logic signal latch condition is that when the logic output L1 is logic H and the clock signal is logic H, the logic signal latch DF / Fs 17, 19, 21, and 23 are latched.
[0099]
The clock signal of the clock circuit 5 is used not only for counting the counters 7 and 28 but also for measuring the delay time between the input pulse and the clock signal.
[0100]
When the pulse input P0 signal is input in a state where the pulse input P1 signal is not input, the logic L0 signal becomes logic H, and this logic L0 signal passes through the delay circuits 10, 12, and 14 and becomes a logic signal latch D-. The latch DF / Fs 16, 18, 20, and 22 are latched under the condition of the logic H of the first clock signal after the pulse input P0 signal is input. Is set to 1.
[0101]
In the logic H of the next clock signal, the pulse input Pl has not been input, and the counter 7 counts up to 2.
[0102]
When the pulse input P1 signal is input and the logic L1 becomes a logic H, the AND gate 6 of the counter input is closed, the counting of the counter 7 is stopped, and at the same time, the logic L1 signal is passed through the delay circuits 11, 13, 15 to the logic L. The signals sequentially become logic H, and the input of the logic conversion DF / F of the pulse input P2 is awaited.
[0103]
Further, in the logic H of the next clock signal, the pulse input P1 signal is input and the logic L1 is at the logic H, so that the latch DF / Fs 17, 19, 21, and 23 are latched, and the counter is further countered. The count of 28 is set to 1.
[0104]
In the logic H of the next clock signal, the pulse input P2 has not been input, and the counter 28 counts up to 2.
[0105]
When the pulse input P2 signal is input and the logic L2 becomes a logic H, the AND gate 27 of the counter input is closed and the counting of the counter 28 is stopped, and at the same time, the logic L2 signal is passed through the delay circuits 34, 35 and 36 to the logic L. The signals sequentially become logic H.
[0106]
In the example of the timing chart, the result of latching the logic signal is that the logic L0 signal, the T / 4 delay signal, the 2T / 4 delay signal, and the 3T / 4 delay signal are all latched by the logic H in the circuit on the pulse input P0 side. In the circuit on the input Pl side, the logic L1 signal and the T / 4 delay signal are latched by logic H, the 2T / 4 delay signal and the 3T / 4 delay signal are latched by logic L, and in the circuit on the pulse input P2 side, the logic L2 signal and The T / 4 delay signal, the 2T / 4 delay signal, and the 3T / 4 delay signal are all logic H.
[0107]
Further, the count values of the counters 7 and 28 are 2.
[0108]
The pulse interval is obtained by adding and subtracting the period T of the clock signal and the logic of the latch circuit.
[0109]
That is, all the latches on the pulse input P0 side are at logic H, which means that 3T / 4 time has elapsed.
[0110]
On the other hand, the pulse input P1 indicates that the 2T / 4 delay signal and the 3T / 4 delay signal are at logic L, and that T / 4 time has elapsed.
[0111]
These latch results are for correcting the count value of the counter 7, and the adder / subtractor 29 obtains 2T + 3T / 4 as an added value from the count 2 of the counter 7 and the latch result on the pulse input P0 side.
[0112]
Next, a result of 2T + 3T / 4−T / 4, that is, a time interval between the pulse input P0 and the pulse input P1 is 2T + 2T / 4 = 2.5T is obtained by subtracting the latch result on the pulse input P1 side.
[0113]
Similarly, the 2T / 4 delay signal and the 3T / 4 delay signal are at logic L on the pulse input Pl side, which means that T / 4 time has elapsed.
[0114]
On the other hand, the latches on the pulse input P2 side are all logic H, which indicates that 3T / 4 time has elapsed.
[0115]
These latch results are for correcting the count value of the counter 28, and the adder 30 obtains a result of 2T + T / 4 from the count 2 of the counter 28 and the latch result on the pulse input P1 side.
[0116]
Next, based on the result of the adder 30 and the latch result on the pulse input P2 side in the subtracter 41, 2T + T / 4-3T / 4, that is, the time interval between the pulse input P1 and the pulse input P2, 2T-2T / 4 = 1. 5T results are obtained.
[0117]
As described above, the delay circuit which divides the pulse interval of the first pulse input P0 signal and the next pulse input P1 signal of the pulse input terminal to be measured and the pulse interval of the next pulse input signal P2 by T / n by the clock period T or less. Is effective in that the pulse input interval of the pulse train can be continuously and accurately measured at a cycle equal to or less than the clock cycle T.
[0118]
In this example, the number of pulse inputs is three, P0, P1, and P2. However, the number of pulse inputs can be increased by increasing the circuit configuration, and the initial pulse input P0 and the next pulse input P1 at the time of interval measurement are further increased. Since it can be used as the next initial pulse, there is an advantage that the number of circuits can be reduced.
[0119]
Further, the processing can be cyclically performed, and the interval between successive pulse inputs can be continuously instrumented by a simple circuit.
[0120]
Even if delay lines, programmable delay lines, logic ICs, print patterns, and the like are configured as delay circuits, and CMOS, ECL, FPGA, and the like are configured as other component circuit devices, measurement can be performed with high accuracy.
[0121]
Embodiment 4 FIG.
Fourth Embodiment A pulse interval measuring circuit according to a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 7 is a diagram showing a configuration of a pulse interval measuring circuit according to Embodiment 4 of the present invention.
[0122]
7, reference numerals 1 and 2 denote DF / Fs for converting a pulse input signal into a logic input signal, 5 a clock circuit for generating a clock signal, 6 an AND gate of the logic input signal and the clock signal, and 7 a clock number. , 8 and 9 are DF / Fs for synchronizing the logic signal input with the clock signal. The DF / Fs 1 and 2 are cascaded as shown in FIG.
[0123]
In the same figure, 10 is a T / 4 delay circuit with a clock signal period T, 12 is a 2T / 4 delay circuit with a clock signal period T, 14 is a 3T / 4 delay circuit with a clock signal period T, 16, Reference numerals 18, 20, and 22 denote DF / Fs for latching delayed logic signals.
[0124]
Further, in the figure, reference numeral 24 denotes an adder for adding the count value of the counter 7 and the outputs of the delay logic signal latch circuits 16, 18, 20, and 22; , 20, 22; a reset circuit 26, which releases the latch by the operation completion signal of the subtractor 25; a register 42, which holds the logic state of the delay circuit; DF / F 44 for generating a signal is an OR gate for generating a latch signal of the delay logic signal latch circuit.
[0125]
Next, the operation of the pulse interval measuring circuit according to the fourth embodiment will be described with reference to the drawings.
[0126]
FIG. 8 is a timing chart showing the operation of the pulse interval measuring circuit according to Embodiment 4 of the present invention.
[0127]
When the measuring circuit is started, a reset signal is sent from the reset circuit 26 to reset all the latches.
[0128]
By the reset, the pulse input DF / F1 is in a state where logic H conversion is possible, and the DF / F2 is in a state where logic H conversion is stopped.
[0129]
When the first pulse input P0 is input to the pulse input terminal to be measured, a logic H signal is output from the logic output L0 by the logic signal conversion DF / F1, and the pulse input DF / F2 is converted to the logic H. It becomes possible.
[0130]
The logic output L0 is input to the AND gate 6, and the counter 7 counts the number of clocks under the condition of three inputs AND of logic H of the logic output L0, logic H without the input of the pulse input P1, and logic H of the clock signal.
[0131]
The logic output L0 passes through the AND gate 6, further passes through the logic signal latching DF / F16, passes through the T / 4 delay circuit 10, passes through the logic signal latching DF / F18, and passes through the 2T / 4 delay circuit 12. The signal is sent to the logic signal latch DF / F 22 and further to the logic signal latch DF / F 22 via the 3T / 4 delay circuit 14.
[0132]
The output of the AND gate 6 is input to the DF / F 8 in order to determine the fraction of the pulse input P0 signal with respect to the clock. When the clock signal becomes logic H, the logic signal is latched through the OR gate 44 by the logic signal latch signal. The delay circuit output logic signal is latched by the signal latch DF / Fs 16, 18, 20, and 22.
[0133]
The logic signal latch signal is provided as a data input signal of the DF / F 43 that generates an ENABLE signal of the register 42.
[0134]
The ENABLE signal sets the ENABLE signal to logic L with a clock signal following the clock signal that generated the logic signal latch signal, and stops reading data into the register 42.
[0135]
Next, when the pulse input P1 is input to the pulse input terminal to be measured, the logic output L1 is a logic H signal from the Q output of the DF / F2 for logic signal conversion, and the logic output (−) is from the (−) Q output. ) L1 outputs logic L. The logic output L1 is sent to a logic signal latch DF / F9. Note that, for example, in (-) Q, (-) represents an overline of Q.
[0136]
The logic output (-) L1 is sent to the logic signal conversion DF / F1, passed through the AND gate 6, passed through the logic signal latch DF / F16, and passed through the T / 4 delay circuit 10 to the logic signal latch. The signal is sent to the logic signal latching DF / F 20 via the DF / F 18 and the 2T / 4 delay circuit 12, and further to the logic signal latching DF / F 22 via the 3T / 4 delay circuit 14.
[0137]
The logic signal latch condition is that when the logic output L1 is logic H and the clock signal is logic H, the logic signal latch DF / Fs 16, 18, 20, and 22 are latched.
[0138]
The clock signal of the clock circuit 5 is used not only for counting by the counter 7 but also for measuring the delay time of the input pulse with respect to the clock signal.
[0139]
When the pulse input P0 signal is input while the pulse input P1 signal is not input, the logic L0 signal becomes logic H, and the logic L0 signal passes through the AND gate 6 and further passes through the delay circuits 10, 12, and 14. The logic signals are input to the DF / Fs 18, 20, and 22 for latching, and the DF / Fs 16, 18, 20, and 22 for latching are input under the condition of the logic H of the first clock signal after the input of the pulse input P0 signal. Latching is performed, and the count of the counter 7 is set to 1.
[0140]
In the logic H of the next clock signal, the pulse input Pl has not been input, and the counter 7 counts up to 2.
[0141]
When the pulse input Pl signal is input and the logic (-) L1 of the (-) Q output of the logic signal conversion DF / F2 becomes logic L, the AND gate 6 of the counter input is closed and the counter 7 counts. At the same time as the stop, the output signal of the AND gate 6 passes through the delay circuits 10, 12, and 14, and the logic signal sequentially becomes logic L.
[0142]
Further, in the logic H of the next clock signal, since the logic L1 is logic H, the logic output of the DF / F9 becomes logic H, and passes through the OR gate 44 to the latch DF / F16, Latch 18, 20, 22. However, since the latched logic signal is performed when the logic of the delay circuit changes from H to L, the direction of the logic level is opposite to that of the first to third embodiments.
[0143]
In the example of the timing chart, the latch result of the logic signal indicates that the logic L0 signal, the T / 4 delay signal, the 2T / 4 delay signal, and the 3T / 4 delay signal are all latched by the logic H in the circuit on the pulse input P0 side. In the circuit on the input Pl side, the logic L1 signal and the T / 4 delay signal are logic L, the 2T / 4 delay signal is logic H, and the 3T / 4 delay signal is logic H.
[0144]
Further, the count value of the counter 7 is 2.
[0145]
The pulse interval is obtained by adding and subtracting the period T of the clock signal and the logic of the latch circuit.
[0146]
That is, all the latches on the pulse input P0 side are at logic H, which means that 3T / 4 time has elapsed.
[0147]
On the other hand, the pulse input P1 side indicates that the 2T / 4 delay signal and the 3T / 4 delay signal are at logic H, and that T / 4 time has elapsed.
[0148]
These latch results are for correcting the count value of the counter 7, and the adder 24 obtains 2T + 3T / 4 from the count 2 of the counter 7 and the latch result on the pulse input P0 side.
[0149]
Next, a result of 2T + 3T / 4-T / 4, that is, 2T + 2T / 4 = 2.5T is obtained from the result of the adder 24 and the latch result on the pulse input P1 side by the subtractor 25.
[0150]
As described above, by using the same delay circuit that divides the pulse interval between the first pulse input P0 signal of the pulse input terminal to be measured and the next pulse input P1 signal by T / n below the clock cycle T, the clock cycle can be increased. There is an effect that measurement can be performed with high accuracy in a cycle of T or less.
[0151]
Even if delay lines, programmable delay lines, logic ICs, print patterns, and the like are configured as delay circuits, and CMOS, ECL, FPGA, and the like are configured as other component circuit devices, measurement can be performed with high accuracy.
[0152]
Embodiment 5 FIG.
Embodiment 5 A pulse interval measuring circuit according to Embodiment 5 of the present invention will be described with reference to the drawings. FIG. 9 is a diagram showing a configuration of a pulse interval measuring circuit according to Embodiment 5 of the present invention.
[0153]
In FIG. 9, reference numerals 1 and 2 denote DF / Fs for converting a pulse input signal into a logic input signal, 5 a clock circuit for generating a clock signal, 6 an AND gate of the logic input signal and the clock signal, and 7 a clock number. , 8 and 9 are DF / Fs for synchronizing the logic signal input with the clock signal. The DF / Fs 1 and 2 are cascaded as shown in FIG.
[0154]
Also, in the figure, reference numerals 10 and 11 denote T / 4 delay circuits having a clock signal period T, 12 and 13 denote 2T / 4 delay circuits having a clock signal period T, and 14 and 15 denote 3T / 3T clock signal periods T. Four delay circuits, 16 to 23, are DF / Fs for latching delayed logic signals.
[0155]
Further, in the figure, reference numeral 24 denotes an adder for adding the count value of the counter 7 to the output of the delay logic signal latch circuits 16, 18, 20, and 22, and 25 denotes a delay logic signal latch circuit 17, 19 from the output of the adder 24. , 21, and 23, a reset circuit 26 for releasing the latch by the operation completion signal of the subtractor 25, a counter 45 for counting the number of clocks, 46 an AND gate for a logic signal and a clock signal, and 47 for A delay circuit 48 for delaying the clock signal is a comparison circuit for comparing the outputs of the counters 7, 45 and the T / 4 delay circuit.
[0156]
Next, the operation of the pulse interval measuring circuit according to the fifth embodiment will be described with reference to the drawings.
[0157]
FIG. 10 is a timing chart showing the operation of the pulse interval measuring circuit according to Embodiment 5 of the present invention.
[0158]
When the measuring circuit is started, a reset signal is sent from the reset circuit 26 to reset all the latches.
[0159]
By the reset, the pulse input DF / F1 is in a state where logic H conversion is possible, and the DF / F2 is in a state where logic H conversion is stopped.
[0160]
When the first pulse input P0 is input to the pulse input terminal to be measured, the logic output L0 outputs a logic H signal by the logic signal conversion DF / F1, and the pulse input DF / F2 changes to the logic H. It will be in a convertible state.
[0161]
The logic output L0 is input to the AND gates 6 and 46, and counts the number of clocks under the conditions of the logic H of the logic output L0, the logic H without the input of the pulse input Pl, and the logic H of the clock signal. Count with. However, the clock signal of the counter 45 is input through a delay circuit that exceeds the T / 4 delay time and is less than the 2T / 4 delay time.
[0162]
The logic output L0 passes through the logic signal latching DF / F16, the T / 4 delay circuit 10, passes through the logic signal latching DF / F18, passes through the 2T / 4 delay circuit 12, and passes through the logic signal latching DF / F. / F20 and further through the 3T / 4 delay circuit 14 to the logic signal latching DF / F22.
[0163]
The logic signal latch condition is that when the logic output L0 is logic H and the clock signal is logic H, the logic signal latch DF / Fs 16, 18, 20, and 22 are latched.
[0164]
Next, when the pulse input Pl is input to the pulse input terminal to be measured, the logic output L1 outputs a logic H signal by the logic signal conversion DF / F2.
[0165]
The logic output L1 is passed through a logic signal latch DF / F 17, a T / 4 delay circuit 11, a logic signal latch DF / F 19, and a logic signal latch DF / F 21 through a 2T / 4 delay circuit 13. The signal is further sent to the logic signal latching DF / F 23 via the 3T / 4 delay circuit 15.
[0166]
The logic signal latch condition is that when the logic output L1 is logic H and the clock signal is logic H, the logic signal latch DF / Fs 17, 19, 21, and 23 are latched.
[0167]
The clock signal of the clock circuit 5 is used not only for counting by the counters 7 and 45 but also for measuring the delay time between the input pulse and the clock signal.
[0168]
When the pulse input P0 signal is input while the pulse input P1 signal is not input, the logic L0 signal becomes logic H, and the logic L0 signal passes through the delay circuits 10, 12, and 14, and the logic signal latch D-F / F18, 20, 22 and latches the DF / Fs 16, 18, 20, 22 for latching under the condition of logic H of the first clock signal after the input of the pulse input P0 signal. Although the count is set to 1, if the logic L0 signal and the clock signal are input simultaneously, the count of the counter 7 becomes indefinite and becomes 1 or 0. However, the counter 45 counts the clock signal input to the counter 7 through the delay circuit 47 by the input and the logic L0 signal through the delay circuit 47. Therefore, there is a time difference between the clock signal and the logic H of the logic L0 signal, and the count is set to 1.
[0169]
In the logic H of the next clock signal, the pulse input P1 is not input, the count of the counter 7 is counted up, and the count becomes 2 or 1. The counter 45 also counts up, and the count becomes 2.
[0170]
When the pulse input P1 signal is input and the logic signal L1 becomes logic H, the AND gates 6, 46 of the counter input are closed, the counting of the counters 7, 45 is stopped, and at the same time, the logic L1 signal is delayed by the delay circuits 11, 13. , And 15 sequentially become logic H.
[0171]
Further, in the logic H of the next clock signal, the pulse input P1 signal is input and the logic L1 is at the logic H, so that the latch DF / Fs 17, 19, 21 and 23 are latched.
[0172]
In the example of the timing chart, the latch result of the logic signal indicates that the logic L0 signal, the T / 4 delay signal, the 2T / 4 delay signal, and the 3T / 4 delay signal are all latched by the logic H in the circuit on the pulse input P0 side. In the circuit on the input P1 side, the logic L1 signal and the T / 4 delay signal are logic H, the 2T / 4 delay signal is logic L, and the 3T / 4 delay signal is logic L.
[0173]
However, when the logic signal H of the pulse input P1 and the clock signal are input at the same time, the count of the counter 7 is uncertain and becomes 2 or 1 or 0. However, since the counter 45 counts the clock signal input to the counter 7 through the delay circuit 47 by the input and the logic H signal of the logic output L1, there is a time difference between the clock signal and the logic H signal of the logic signal L1, and the counting is performed. Let it be 2.
[0174]
The comparison circuit 48 is an arithmetic circuit for using a correct count when a mismatch occurs between the count values of the counter 7 and the counter 45, and performs the following operation.
[0175]
In the above example, the logic H signal of the pulse input P0 and the clock signal are input simultaneously, and the logic H signal of the pulse input P1 and the clock signal are input simultaneously, and the count value of the counter 7 becomes indefinite. Since the / 4 delay signal is a logic L signal for both the logic L0 signal and the logic L1 signal, when the T / 4 delay signal is logic L for both the logic L0 and L1 signals, the addition / subtraction operation is performed using the count value of the counter 45. .
[0176]
When the logic H signal of the pulse input P0 and the clock signal passing through the delay circuit 47 are input simultaneously, and the logic H signal of the pulse input P1 and the clock signal passing through the delay circuit 47 are input simultaneously, the count value of the counter 45 is undefined. However, since the T / 4 delay signal is a logic L signal and the logic L1 signal is a logic H signal, the count value of the counter 7 is used when the T / 4 delay signal is a logic H signal for both the logic signals L0 and L1. And add / subtract.
[0177]
However, the logic H signal of the pulse input P0 and the clock signal are input simultaneously, the logic H signal of the pulse input P1 and the clock signal passed through the delay circuit 47 are input simultaneously, and the logic H signal of the pulse input P0 and the delay circuit 47 are input. When the clock signal that has passed through is input simultaneously and the logic H signal of the pulse input P1 and the clock signal are simultaneously input, the count value of the counter 7 or the counter 45 becomes indefinite, and the logic L0 signal of the T / 4 delay signal and the logic Since the logic signal of the L1 signal does not match and cannot be counted, it is output as an error.
[0178]
The pulse interval is obtained by adding and subtracting the period T of the clock signal and the logic of the latch circuit.
[0179]
That is, all the latches on the pulse input P0 side are at logic H, which means that 3T / 4 time has elapsed.
[0180]
On the other hand, the pulse input P1 indicates that the 2T / 4 delay signal and the 3T / 4 delay signal are at logic L, and that T / 4 time has elapsed.
[0181]
These latch results are for correcting the count value of the counter 7, and the adder 24 obtains 2T + 3T / 4 from the count 2 of the counter 7 and the latch result on the pulse input P0 side.
[0182]
Next, a result of 2T + 3T / 4-T / 4, that is, 2T + 2T / 4 = 2.5T is obtained from the result of the adder 24 and the latch result on the pulse input P1 side by the subtractor 25.
[0183]
As described above, when the count value of the counter that counts the clock signal is uncertain, an error is output, and there is an effect of eliminating the uncertain value.
[0184]
Even if delay lines, programmable delay lines, logic ICs, print patterns, and the like are configured as delay circuits, and CMOS, ECL, FPGA, and the like are configured as other component circuit devices, measurement can be performed with high accuracy.
[0185]
Embodiment 6 FIG.
Embodiment 6 A pulse interval measuring circuit according to Embodiment 6 of the present invention will be described with reference to the drawings. FIG. 11 is a diagram showing a configuration of a pulse interval measuring circuit according to Embodiment 6 of the present invention.
[0186]
In FIG. 11, reference numerals 1 and 2 denote DF / Fs for converting a pulse input signal into a logic input signal, 5 a clock circuit for generating a clock signal, 6 an AND gate of the logic input signal and the clock signal, and 7 a clock number. , 8 and 9 are DF / Fs for synchronizing the logic signal input with the clock signal. The DF / Fs 1 and 2 are cascaded as shown in FIG.
[0187]
Also, in the figure, reference numerals 10 and 11 denote T / 4 delay circuits having a clock signal period T, 12 and 13 denote 2T / 4 delay circuits having a clock signal period T, and 14 and 15 denote 3T / 3T clock signal periods T. Four delay circuits, 16 to 23, are DF / Fs for latching delayed logic signals.
[0188]
Further, in the figure, reference numeral 24 denotes an adder for adding the count value of the counter 7 to the output of the delay logic signal latch circuits 16, 18, 20, and 22, and 25 denotes a delay logic signal latch circuit 17, 19 from the output of the adder 24. , 21 and 23, 26 is a reset circuit for releasing the latch by the operation completion signal of the subtractor 25, 45 and 49 are counters for counting the number of clocks, and 46 and 50 are AND of the logic signal and the clock signal. Gates, 47 and 51, delay circuits for delaying the clock signal, and 48, a counter circuit for comparing the logic outputs of the counters 7, 45, 49 and the T / 4 delay circuit and the 2T / 4 delay circuit.
[0189]
Next, the operation of the pulse interval measuring circuit according to the sixth embodiment will be described with reference to the drawings.
[0190]
FIG. 12 is a timing chart showing the operation of the pulse interval measuring circuit according to Embodiment 6 of the present invention.
[0191]
When the measuring circuit is started, a reset signal is sent from the reset circuit 26 to reset all the latches.
[0192]
By the reset, the pulse input DF / F1 is in a state where logic H conversion is possible, and the DF / F2 is in a state where logic H conversion is stopped.
[0193]
When the first pulse input P0 is input to the pulse input terminal to be measured, the logic output L0 outputs a logic H signal by the logic signal conversion DF / F1, and the pulse input DF / F2 changes to the logic H. It will be in a convertible state.
[0194]
The logic output L0 is input to AND gates 6, 46, and 50, and the counter 7 counts the number of clocks under the conditions of logic H of the logic output L0, logic H without the input of the pulse input P1, and logic H of the clock signal. , 45, 49. However, the clock signal of the counter 45 exceeds the T / 4 delay time and is input through the delay circuit 47 of less than the 2T / 4 delay time, and the clock signal of the counter 49 similarly exceeds the T / 4 delay time and is 2T / 4. It is input through a delay circuit 51 shorter than the delay time.
[0195]
The logic output L0 passes through the logic signal latching DF / F16, the T / 4 delay circuit 10, passes through the logic signal latching DF / F18, passes through the 2T / 4 delay circuit 12, and passes through the logic signal latching DF / F. / F20 and further through the 3T / 4 delay circuit 14 to the logic signal latching DF / F22.
[0196]
The logic signal latch condition is that when the logic output L0 is logic H and the clock signal is logic H, the logic signal latch DF / Fs 16, 18, 20, and 22 are latched.
[0197]
Next, when the pulse input Pl is input to the pulse input terminal to be measured, the logic output L1 outputs a logic H signal by the logic signal conversion DF / F2.
[0198]
The logic output L1 is passed through a logic signal latch DF / F 17, a T / 4 delay circuit 11, a logic signal latch DF / F 19, and a logic signal latch DF / F 21 through a 2T / 4 delay circuit 13. The signal is further sent to the logic signal latching DF / F 23 via the 3T / 4 delay circuit 15.
[0199]
The logic signal latch condition is that when the logic output L1 is logic H and the clock signal is logic H, the logic signal latch DF / Fs 17, 19, 21, and 23 are latched.
[0200]
The clock signal of the clock circuit 5 is used not only for counting by the counters 7, 45, and 49, but also for measuring the delay time between the input pulse and the clock signal.
[0201]
When the pulse input P0 signal is input while the pulse input P1 signal is not input, the logic L0 signal becomes logic H, and the logic L0 signal passes through the delay circuits 10, 12, and 14, and the logic signal latch D-F / F18, 20, 22 and latches the DF / Fs 16, 18, 20, 22 for latching under the condition of logic H of the first clock signal after the input of the pulse input P0 signal. Although the count is set to 1, if the logic L0 signal and the clock signal are input simultaneously, the count of the counter 7 becomes indefinite and becomes 1 or 0.
[0202]
However, the counter 45 counts the clock signal input to the counter 7 through the delay circuit 47 by the input and the logic L0 signal through the delay circuit 47. Therefore, there is a time difference between the clock signal and the logic H signal of the logic output L0, and the counter is set to 1. The count 49 is set to 1 as in the counter 45. In the logic H of the next clock signal, the pulse input P1 is not input, and the count of the counter 7 is counted up, and the count becomes 2 or 1. The counters 45 and 49 also count up, and the count becomes 2.
[0203]
When the pulse input P1 signal is input and the logic L1 becomes logic H, the AND gate 6 of the counter input is closed, the counting of the counters 7 and 45 is stopped, and at the same time, the logic L1 signal is applied to the delay circuits 11, 13, and 15. After that, the logic signals sequentially become logic H.
[0204]
Further, in the logic H of the next clock signal, the pulse input Pl signal is input and the logic L1 is in the logic H, so that the latch DF / Fs 17, 19, 21, and 23 are latched.
[0205]
In the example of the timing chart, the latch result of the logic signal indicates that the logic L0 signal, the T / 4 delay signal, the 2T / 4 delay signal, and the 3T / 4 delay signal are all latched by the logic H in the circuit on the pulse input P0 side. In the circuit on the input Pl side, the logic L1 signal and the T / 4 delay signal are logic H, the 2T / 4 delay signal is logic L, and the 3T / 4 delay signal is logic L.
[0206]
However, when the logic signal H of the pulse input P1 and the clock signal passed through the delay circuit 47 are input at the same time, the count of the counter 45 becomes indefinite and becomes 3 or 2. However, since the counter 49 counts the clock signal input to the counter 45 through the delay circuit 51 by the input and the logic H signal of the logic output L1, there is a time difference between the clock signal and the logic H signal of the logic output L1, and the counting is performed. Let it be 2.
[0207]
The comparison circuit 48 is an arithmetic circuit for using a correct count when the count values of the counter 7, the counter 45, and the counter 47 do not match, and performs the following operation.
[0208]
In the above example, the logic H signal of the pulse input P0 and the clock signal are input simultaneously, and the logic H signal of the pulse input P1 and the clock signal passed through the delay circuit 47 are input simultaneously. Is uncertain, but the T / 4 delay signal is a logic L signal with a logic L0 signal, the 2T / 4 delay signal is a logic L signal with a logic L0 signal, the T / 4 delay signal is a logic L signal with a logic L1 signal, and 2T Since the / 4 delay signal is a logic L1 signal and a logic H signal, when this condition is satisfied, the addition / subtraction operation is performed using the count value of the counter 49.
[0209]
From the combination of the simultaneous input of the logic signals L0 and L1 of the pulse inputs P0 and P1 and the clock signal, the clock signal passed through the delay circuit 47 and the clock signal passed through the delay circuit 51, the following combinations other than the above are as follows.
[0210]
The T / 4 delay signal is a logic L signal with a logic L0 signal, the 2T / 4 delay signal is a logic L signal with a logic L0 signal, the T / 4 delay signal is a logic L signal with a logic L1 signal, and the 2T / 4 delay signal is a logic L1. When the signal is a logic L signal, the count value of the counter 49 is used.
[0211]
The T / 4 delay signal is a logic L signal with a logic L0 signal, the 2T / 4 delay signal is a logic L signal with a logic L0 signal, the T / 4 delay signal is a logic H signal with a logic L1 signal, and the 2T / 4 delay signal is a logic L1. When the signal is a logic L signal, the count of the counter 45 is (count value-1).
[0212]
The T / 4 delay signal is a logic L signal with a logic L0 signal, the 2T / 4 delay signal is a logic L signal with a logic L0 signal, the T / 4 delay signal is a logic L signal with a logic L1 signal, and the 2T / 4 delay signal is a logic L1. When the signal is a logic L signal, the count value of the counter 45 is used.
[0213]
The T / 4 delay signal is a logic L signal with a logic L0 signal, the 2T / 4 delay signal is a logic L signal with a logic L0 signal, the T / 4 delay signal is a logic H signal with a logic L1 signal, and the 2T / 4 delay signal is a logic L1. When the signal is a logic L signal, the count value of the counter 45 is used.
[0214]
The T / 4 delay signal is a logic L signal with a logic L0 signal, the 2T / 4 delay signal is a logic L signal with a logic L0 signal, the T / 4 delay signal is a logic H signal with a logic L1 signal, and the 2T / 4 delay signal is a logic L1. When the signal is a logic H signal, the count of the counter 7 is (count value-1).
[0215]
The T / 4 delay signal is a logic H signal with a logic L0 signal, the 2T / 4 delay signal is a logic H signal with a logic L0 signal, the T / 4 delay signal is a logic L signal with a logic L1 signal, and the 2T / 4 delay signal is a logic L1. When the signal is a logic L signal, the count of the counter 49 is (count value-1).
[0216]
The T / 4 delay signal is a logic L signal with a logic L0 signal, the 2T / 4 delay signal is a logic H signal with a logic L0 signal, the T / 4 delay signal is a logic H signal with a logic L1 signal, and the 2T / 4 delay signal is a logic L1. When the signal is a logic L signal, the count value of the counter 7 is used.
[0219]
The T / 4 delay signal is a logic L signal with a logic L0 signal, the 2T / 4 delay signal is a logic H signal with a logic L0 signal, the T / 4 delay signal is a logic H signal with a logic L1 signal, and the 2T / 4 delay signal is a logic L1. When the signal is a logic H signal, the count value of the counter 7 is used.
[0218]
The pulse interval is obtained by adding and subtracting the period T of the clock signal and the logic of the latch circuit.
[0219]
That is, all the latches on the pulse input P0 side are at logic H, which means that 3T / 4 time has elapsed.
[0220]
On the other hand, the pulse input P1 indicates that the 2T / 4 delay signal and the 3T / 4 delay signal are at logic L, and that T / 4 time has elapsed.
[0221]
These latch results are for correcting the count value of the counter 7, and the adder 24 obtains 2T + 3T / 4 from the count 2 of the counter 7 and the latch result on the pulse input P0 side.
[0222]
Next, a result of 2T + 3T / 4-T / 4, that is, 2T + 2T / 4 = 2.5T is obtained from the result of the adder 24 and the latch result on the pulse input P1 side by the subtractor 25.
[0223]
As described above, when the count value of the counter that counts the clock signal is uncertain, the comparison circuit 48 that compares the logic level of the delay circuit and calculates with the accurate count value is provided, which has the effect of enabling accurate measurement. .
[0224]
As the delay circuit, a delay line, a programmable delay line, a logic IC, a print pattern, and the like can be measured with high accuracy even if the device is configured with a CMOS, ECL, FPGA, or the like as another component circuit device.
[0225]
【The invention's effect】
As described above, the pulse interval measuring circuit according to the present invention includes a clock circuit for generating a clock signal, a DF / F for initial pulse for converting an initial pulse input into an initial logic signal, and a next logic for inputting the next pulse. The next pulse DF / F to be converted into a signal, the initial logic signal, the next logic signal when there is no next pulse input, and the number of clocks of the clock signal when the clock signal is logic H are counted. A counter for stopping the counting when the next pulse is input, a DF / F for initial logic for synchronizing the initial logic signal with the clock signal, and synchronizing the next logic signal with the clock signal. The next logic DF / F to be synchronized, and a delay obtained by dividing the synchronized initial logic signal into equal periods of the clock signal. An initial pulse delay circuit for sequentially delaying the synchronized next logic signal, a next pulse delay circuit for sequentially delaying the synchronized next logic signal by a delay obtained by equally dividing the cycle of the clock signal, and latching the delayed initial logic signal. DF / F for initial logic signal latch, DF / F for next logic signal latch for latching the delayed next logic signal, DF / F for the count value of the counter, and DF / F for initial logic signal latch And an subtractor that subtracts the output of the next logic signal latch DF / F from the output of the adder to calculate the pulse interval of the initial and next pulse inputs. This has the effect that the pulse interval can be measured with high accuracy at a cycle equal to or less than the cycle of the clock signal.
[0226]
Further, as described above, the pulse interval measurement circuit according to the present invention cascade-connects the DF / F for the initial pulse and the DF / F for the next pulse. This has the effect that the pulse interval can be measured with high accuracy.
[0227]
Further, as described above, the pulse interval measuring circuit according to the present invention includes a clock circuit for generating a clock signal, a DF / F for initial pulse for converting an initial pulse input into an initial logic signal, and a next pulse input. A next pulse DF / F for converting to a next logic signal, a third pulse DF / F for converting a third pulse input to a third logic signal, and no initial logic signal and no next pulse input A first counter that counts the number of clocks of the clock signal when the next logic signal and the clock signal are at logic H, and stops counting when the next pulse is input; Signal, a third logic signal in the absence of the third pulse input, and a clock of the clock signal when the clock signal is logic H A second counter for stopping the counting when the third pulse input is present; a DF / F for initial logic for synchronizing the initial logic signal with the clock signal; A DF / F for next logic for synchronizing a signal with the clock signal, a DF / F for third logic for synchronizing the third logic signal with the clock signal, and the clock for the synchronized initial logic signal. An initial pulse delay circuit for sequentially delaying the signal cycle by an equal delay, a next pulse delay circuit for sequentially delaying the synchronized next logic signal by an equal delay of the clock signal cycle, A third pulse delay circuit for sequentially delaying the synchronized third logic signal by a delay obtained by equally dividing the cycle of the clock signal; DF / F for latching the initial logic signal, latching the delayed logic signal, DF / F for latching the delayed next logic signal, and a third latching the delayed third logic signal. A logic signal latch DF / F, a count value of the first counter, and an output of the initial logic signal latch DF / F are added, and the next logic signal latch DF is added based on the added value. / F for subtracting the output of / F to calculate the pulse interval of the initial and next pulse input, and an adder for adding the count value of the second counter and the output of the next logic signal latch DF / F. And a subtractor for subtracting the output of the third logic signal latch DF / F from the output of the adder to calculate the pulse interval of the next and third pulse inputs, so that the clock signal This has the effect that the pulse interval can be measured with high accuracy in a cycle shorter than the cycle of.
[0228]
Further, as described above, the pulse interval measurement circuit according to the present invention eliminates the next-pulse delay circuit, and the initial-pulse delay circuit converts the synchronized initial and next logic signals to the cycle of the clock signal. The next logic signal latch DF / F is deleted sequentially by the equal delay, and the initial logic signal latch DF / F latches the delayed initial and next logic signals. The adder adds the count value of the counter and the latched initial logic signal, and the subtractor subtracts the latched next logic signal from the output of the adder to generate the initial and next pulse inputs. Since the pulse interval is calculated and the delay circuit for the initial pulse and the next pulse is shared, the pulse interval can be measured with high accuracy in a cycle shorter than the cycle of the clock signal. There is an effect that that.
[0229]
Further, as described above, the pulse interval measuring circuit according to the present invention may be configured such that the initial logic signal, the next logic signal when there is no next pulse input, and the clock of the clock signal when the delayed clock signal is logic H. A second counter for counting the number and stopping the count when the next pulse input is present, and outputting an error when the count values of the counter and the second counter are indeterminate And the pulse interval can be measured with high accuracy in a cycle shorter than the cycle of the clock signal.
[0230]
Further, as described above, the pulse interval measurement circuit according to the present invention is configured such that when the initial logic signal, the next logic signal in the absence of the next pulse input, and the clock signal delayed by the first time are logic H, A second counter that counts the number of clocks of the clock signal and stops the counting when the next pulse input is present, the initial logic signal, the next logic signal when the next pulse input is absent, and A third counter for counting the number of clocks of the clock signal when the clock signal delayed by the second time is logic H, and stopping the counting when the next pulse is input; The counter, the second counter, or the third counter based on a predetermined condition of the output of the signal latch DF / F. A comparison circuit that outputs any one of the count values of the counter to the adder; and the adder adds the output of the comparison circuit and the output of the initial logic signal latch DF / F. There is an effect that the pulse interval can be measured with high accuracy in a cycle shorter than the cycle of the clock signal.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a pulse interval measurement circuit according to Embodiment 1 of the present invention.
FIG. 2 is a timing chart showing an operation of the pulse interval measuring circuit according to the first embodiment of the present invention.
FIG. 3 is a diagram showing a configuration of a pulse interval measuring circuit according to a second embodiment of the present invention.
FIG. 4 is a timing chart showing an operation of the pulse interval measuring circuit according to the second embodiment of the present invention.
FIG. 5 is a diagram showing a configuration of a pulse interval measuring circuit according to Embodiment 3 of the present invention.
FIG. 6 is a timing chart showing an operation of the pulse interval measuring circuit according to Embodiment 3 of the present invention.
FIG. 7 is a diagram showing a configuration of a pulse interval measuring circuit according to a fourth embodiment of the present invention.
FIG. 8 is a timing chart showing an operation of the pulse interval measuring circuit according to Embodiment 4 of the present invention.
FIG. 9 is a diagram showing a configuration of a pulse interval measuring circuit according to a fifth embodiment of the present invention.
FIG. 10 is a timing chart showing an operation of the pulse interval measuring circuit according to the fifth embodiment of the present invention.
FIG. 11 is a diagram showing a configuration of a pulse interval measurement circuit according to Embodiment 6 of the present invention.
FIG. 12 is a timing chart showing an operation of the pulse interval measuring circuit according to Embodiment 6 of the present invention.
FIG. 13 is a diagram showing a configuration of a conventional pulse interval measurement circuit.
FIG. 14 is a timing chart showing the operation of a conventional pulse interval measurement circuit.
[Explanation of symbols]
1, 2 DF / F, 3, 4 delay circuit, 5 clock circuit, 6 AND gate, 7 counter, 8, 9 DF / F, 10, 11 T / 4 delay circuit, 12, 132T / 4 Delay circuit, 14, 15 3T / 4 delay circuit, 16 to 23 DF / F, 24 adder, 25 subtractor, 26 reset circuit, 27 AND gate, 28 counter, 29 adder / subtracter, 30 adder, 31D -F / F, 32 delay circuits, 33 DF / F, 34 T / 4 delay circuits, 352 T / 4 delay circuits, 363 T / 4 delay circuits, 37 to 40 DF / F, 41 subtractor, 42 registers, 43 DF / F, 44 OR gate, 45 counter, 46 AND gate, 47 delay circuit, 48 comparison circuit, 49 counter, 50 AND gate, 51 delay circuit.

Claims (6)

A clock circuit for generating a clock signal;
An initial pulse DF / F for converting an initial pulse input into an initial logic signal;
A next pulse DF / F for converting the next pulse input into the next logic signal;
The initial logic signal, the next logic signal when there is no next pulse input, and the number of clocks of the clock signal when the clock signal is logic H, and the count when there is the next pulse input. A counter to stop,
An initial logic DF / F for synchronizing the initial logic signal with the clock signal;
A next logic DF / F for synchronizing the next logic signal with the clock signal;
An initial pulse delay circuit for sequentially delaying the synchronized initial logic signal by a delay obtained by equally dividing the cycle of the clock signal;
A next pulse delay circuit for sequentially delaying the synchronized next logic signal by a delay obtained by equally dividing the cycle of the clock signal;
An initial logic signal latch DF / F for latching the delayed initial logic signal;
A next logic signal latch DF / F for latching the delayed next logic signal;
An adder for adding the count value of the counter and the output of the initial logic signal latch DF / F;
A pulse interval measuring circuit, comprising: a subtracter for subtracting an output of the next logic signal latch DF / F from an output of the adder to calculate a pulse interval between the initial and next pulse inputs. 2. The pulse interval measuring circuit according to claim 1, wherein the DF / F for the initial pulse and the DF / F for the next pulse are cascaded. A clock circuit for generating a clock signal;
An initial pulse DF / F for converting an initial pulse input into an initial logic signal;
A next pulse DF / F for converting the next pulse input into the next logic signal;
A third pulse DF / F for converting the third pulse input into a third logic signal;
The initial logic signal, the next logic signal in the absence of the next pulse input, and the number of clocks of the clock signal when the clock signal is logic H, and the count in the case of the next pulse input. A first counter to stop;
When the next logic signal, the third logic signal when there is no third pulse input, and the clock signal are logic H, the number of clocks of the clock signal is counted, and when the third pulse input is present, A second counter for stopping the counting;
An initial logic DF / F for synchronizing the initial logic signal with the clock signal;
A next logic DF / F for synchronizing the next logic signal with the clock signal;
A third logic DF / F for synchronizing the third logic signal with the clock signal;
An initial pulse delay circuit for sequentially delaying the synchronized initial logic signal by a delay obtained by equally dividing the cycle of the clock signal;
A next pulse delay circuit for sequentially delaying the synchronized next logic signal by a delay obtained by equally dividing the cycle of the clock signal;
A third pulse delay circuit for sequentially delaying the synchronized third logic signal by a delay obtained by equally dividing the cycle of the clock signal;
An initial logic signal latch DF / F for latching the delayed initial logic signal;
A next logic signal latch DF / F for latching the delayed next logic signal;
A third logic signal latch DF / F for latching the delayed third logic signal;
The count value of the first counter is added to the output of the initial logic signal latch DF / F, and the output of the next logic signal latch DF / F is subtracted from the added value to obtain the initial and next output values. An adder / subtractor that calculates a pulse interval of a pulse input;
An adder for adding the count value of the second counter and the output of the next logic signal latch DF / F;
And a subtractor for subtracting an output of the third logic signal latch DF / F from an output of the adder to calculate a pulse interval of the next and third pulse inputs. circuit. Delete the next pulse delay circuit,
The initial pulse delay circuit sequentially delays the synchronized initial and next logic signals by a delay obtained by equally dividing the cycle of the clock signal,
Deleting the next logic signal latch DF / F,
The initial logic signal latch DF / F latches the delayed initial and next logic signals,
The adder adds the count value of the counter and the latched initial logic signal,
The subtractor subtracts the latched next logic signal from the output of the adder to calculate a pulse interval of the initial and next pulse inputs,
3. The pulse interval measuring circuit according to claim 2, wherein a delay circuit for the initial pulse and a delay circuit for the next pulse are shared. The number of clocks of the clock signal is counted when the initial logic signal, the next logic signal in the absence of the next pulse input, and the delayed clock signal are logic H, and the count is performed in the presence of the next pulse input. A second counter to stop
3. The pulse interval measurement circuit according to claim 2, further comprising: a comparison circuit that outputs an error when the count values of the counter and the second counter are uncertain. When the initial logic signal, the next logic signal in the absence of the next pulse input, and the clock signal delayed by the first time are logic H, the number of clocks of the clock signal is counted, and the presence of the next pulse input is counted. A second counter for stopping the counting in case
When the initial logic signal, the next logic signal in the absence of the next pulse input, and the clock signal delayed by the second time are logic H, the number of clocks of the clock signal is counted, and the presence of the next pulse input is counted. A third counter for stopping the counting in the case;
One of the counter, the second counter, and the third counter is output to the adder based on a predetermined condition of the output of the initial and next logic signal latch DF / F. And a comparing circuit that performs
3. The pulse interval measurement circuit according to claim 2, wherein the adder adds an output of the comparison circuit and an output of the initial logic signal latch DF / F.

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