CN104485932B - External trigger pulse width predicting circuit - Google Patents
External trigger pulse width predicting circuit Download PDFInfo
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- CN104485932B CN104485932B CN201410654340.6A CN201410654340A CN104485932B CN 104485932 B CN104485932 B CN 104485932B CN 201410654340 A CN201410654340 A CN 201410654340A CN 104485932 B CN104485932 B CN 104485932B
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Abstract
The invention relates to an external trigger pulse width predicting circuit, and solves the technical problems of deterioration of a signal pulse width and an edge signal of existing pulse signals during transmission process. The external trigger pulse width predicting circuit comprises a pulse input unit, a pulse delay unit, a pulse prognosis processing unit and a pulse output unit; the output end of the pulse input unit is divided into two paths, one path is connected with the input end of the pulse delay unit, the other path is connected with the input end of the pulse prognosis processing unit, the output end of the pulse delay unit is connected with the input end of the pulse prognosis processing unit, and the output end of the pulse prognosis processing unit is connected with the input end of the pulse output unit. The external trigger pulse width predicting circuit is used widely for generation and transmission of pulse signals.
Description
Technical field
The present invention relates to a kind of pulse signal transmission circuit, specifically a kind of external trigger pulsewidth prediction circuit.
Background technology
Pulse signal, as a kind of common signal form, is widely used in various systems and controls in link.As
, along information such as times, when transmitting in a link, these information are often because signal passes for the important pulsewidth of pulse signal, rise/fall
The composite factors such as defeated line parasitic parameter, joint reflection affect and lead to deterioration information, cause the exception of subsequent treatment.
Content of the invention
The present invention is exactly to solve signal pulsewidth in transmitting procedure for the existing pulse signal and along signal degradation problems
Technical problem, provide a kind of prevent pulse signal in transmitting procedure signal pulsewidth and along signal deteriorate external trigger pulsewidth pre-
Slowdown monitoring circuit.
The technical scheme is that, a kind of external trigger pulsewidth prediction circuit is provided, prolongs including pulse input unit, pulse
Unit, pulse anticipation processing unit and pulse output unit late；The outfan of pulse input unit divides two-way, and a road and pulse are prolonged
The input of unit connects late, and another road is connected with the input of pulse anticipation processing unit；The outfan of pulse delay unit
It is connected with the input of pulse anticipation processing unit, the outfan of pulse anticipation processing unit and the input of pulse output unit
Connect；
The pulse signal that pulse delay unit is configured to send pulse input unit is divided into serial time delayed signal；
Pulse anticipation processing unit includes time delay Acquisition Circuit, delay stages number encoder circuit and pulse output anticipation circuit,
Time delay Acquisition Circuit includes d type flip flop and XOR gate；The serial time delay that described pulse delay unit is exported by time delay Acquisition Circuit
Signal is respectively supplied to corresponding d type flip flop, as the triggering collection signal to pulse input unit, and by its corresponding logic
0 or logic 1 be supplied to delay stages number encoder circuit and encoded, simultaneously adjacent state value as the input signal of XOR gate,
The output signal of XOR gate is supplied to delay stages number encoder circuit as Rule of judgment, and time delay is gathered by delay stages number encoder circuit
The state encoding of circuit is supplied to pulse output anticipation circuit, and pulse output anticipation circuit is according to coding, fixed delay and known
Pulse signal is determined as pulse output unit and provides pulse signal.
Preferably, pulse delay unit is delay buffer, DS1100-T chip or delay line.
The invention has the beneficial effects as follows, realize pulse-width and judge, same pulse width and higher-quality edge are provided
Information；The system used time is decreased as Rule of judgment using XOR.Meanwhile, this invention system structure is simple, low cost, just
In realization and control.
Further aspect of the present invention and aspect, by the description below with reference to the specific embodiment of accompanying drawing, are able to
It is clearly stated that.
Brief description
Fig. 1 is the theory diagram of the present invention；
Fig. 2 is the theory diagram of pulse delay unit；
Fig. 3 is the circuit diagram that pulse delay unit adopts delay buffer；
Fig. 4 is the circuit diagram that pulse delay unit adopts delay chip；
Fig. 5 is the theory diagram of pulse anticipation processing unit；
Fig. 6 is workflow diagram.
In figure symbol description：
1. pulse input unit；2. pulse delay unit；3. pulse anticipation processing unit；4. pulse output unit；5. τ prolongs
Buffer late；6.D trigger；7. XOR gate；8. delay stages number encoder circuit；9. pulse output anticipation circuit.
Specific embodiment
Referring to the drawings, with specific embodiment, the present invention is described in further detail.
As shown in figure 1, the present invention includes pulse input unit 1, pulse delay unit 2, pulse anticipation processing unit 3 and arteries and veins
Rush output unit 4.The outfan of pulse input unit 1 divides two-way, and a road is connected with the input of pulse delay unit 2, another
Road is connected with the input of pulse anticipation processing unit 3.The outfan of pulse delay unit 2 and pulse anticipation processing unit 3
Input connects, and the outfan of pulse anticipation processing unit 3 is connected with the input of pulse output unit 4.
As shown in Fig. 2 the pulse signal that pulse input unit 1 is sent by pulse delay unit 2 is in units of constant time lag τ
Carry out delay process, formed n (>1) time delayed signal of individual series.
As shown in figure 3, pulse delay unit 2 specifically can be realized by the buffer of PLD.Input pulse
Export as time delay τ after one group of τ delay buffer 5, this delay τ output simultaneously is as the input of later group τ delay buffer
Signal obtains time delay 2 τ output, until obtaining time delay n τ output.
As shown in figure 4, pulse delay unit 2 specifically can also be realized by delay chip.Taking 5 grades of time delays as a example, time delay
Chip concrete model can adopt DS1100-T chip, and T is total delay time.The IN pin of input pulse and DS1100-T chip
Connect, time delay T/5 pulse signal Output_T/5 is exported by the TAP1 pin of DS1100-T chip, time delay 2*T/5 pulse signal
Output_2*T/5 by DS1100-T chip TAP2 pin export, time delay 3*T/5 pulse signal Output_3*T/5 by
The TAP3 pin output of DS1100-T chip, time delay 4*T/5 pulse signal Output_4*T/5 is by the TAP4 of DS1100-T chip
Pin exports, and time delay T pulse signal Output_T is exported by the TAP5 pin of DS1100-T chip, the VCC of DS1100-T chip
Pin connects power supply+5V, the GND pin ground connection of DS1100-T chip.
Additionally, pulse delay unit 2 can also be realized by delay line.
As shown in figure 5, pulse anticipation processing unit 3 to include time delay Acquisition Circuit, delay stages number encoder circuit 8 and pulse defeated
Go out anticipation circuit 9, time delay Acquisition Circuit includes d type flip flop 6 and XOR gate 7.Pulse delay unit 2 is exported by time delay Acquisition Circuit
Serial time delayed signal be respectively supplied to corresponding d type flip flop 6, as the triggering collection signal to same pulse input unit 1,
And its corresponding state value " 0 " or " 1 " are supplied to follow-up delay stages number encoder circuit 8 are encoded, simultaneously adjacent shape
State value is supplied to follow-up time delay series as Rule of judgment and compiles as the input signal of XOR gate 7, the output signal of XOR gate 7
Code circuit 8, the state encoding of time delay Acquisition Circuit is supplied to pulse output anticipation circuit 9, pulse by delay stages number encoder circuit 8
Output anticipation circuit 9 is determined as pulse output unit 4 according to coding, fixed delay and known pulse signal and provides pulse signal.
As shown in fig. 6, the pulse parameter forming process of pulse signal is as follows：
Step one, power-up initializing, complete pulse width, unit time delay setting, and pulse width T that prestoresPFor 0.
Step 2, the XOR gate logic output signal Px (x is 1,2 ..., n-1) of pulse anticipation processing unit 3 are as entering
The trigger condition of row coding, when it is 1, D1～Dx that d type flip flop 6 is exported is encoded, and otherwise, continues waiting for.
The coding that step 2 is exported by step 3, the delay stages number encoder circuit 8 of pulse anticipation processing unit 3 with right before
Ratio if identical, exports the pulse signal of width as before, otherwise carries out pulse width inquiry and configuration operation.Arteries and veins
Rush width TRDetermined by formula (1), pulse width inquiry and configuration pulse width will be more than TRAnd immediate width is as defeated
Go out parameter, give pulse width T that prestoresP?.
TR=[Dx*2^ (x-1)+D (x-1) * 2^ (x-2)+... D1*2^0] * τ (1)
The above, only to the preferred embodiments of the present invention, is not limited to the present invention, for the skill of this area
For art personnel, the present invention can have various modifications and variations.Every claim in the present invention is done in the range of limiting
Any modification, equivalent substitution and improvement etc., all should be within protection scope of the present invention.
Claims (2)
1. a kind of external trigger pulsewidth prediction circuit, is characterized in that, including pulse input unit, pulse delay unit, pulse anticipation
Processing unit and pulse output unit；The outfan of described pulse input unit divides two-way, a road and described pulse delay unit
Input connect, another road is connected with the input of described pulse anticipation processing unit；The output of described pulse delay unit
End is connected with the input of described pulse anticipation processing unit, and the outfan of described pulse anticipation processing unit is defeated with described pulse
The input going out unit connects；
The pulse signal that described pulse delay unit is configured to send described pulse input unit is divided into serial time delayed signal；
Described pulse anticipation processing unit includes time delay Acquisition Circuit, delay stages number encoder circuit and pulse output anticipation circuit,
Described time delay Acquisition Circuit includes d type flip flop and XOR gate；Described pulse delay unit is exported by described time delay Acquisition Circuit
Serial time delayed signal is respectively supplied to corresponding d type flip flop, as the triggering collection signal to described pulse input unit, and will
Its corresponding logical zero or logic 1 are supplied to described delay stages number encoder circuit and are encoded, and simultaneously adjacent state value is as institute
State the input signal of XOR gate, the output signal of described XOR gate is supplied to described delay stages number encoder electricity as Rule of judgment
Road, the state encoding of described time delay Acquisition Circuit is supplied to described pulse output anticipation electricity by described delay stages number encoder circuit
Road, described pulse output anticipation circuit is determined as described pulse output unit according to coding, fixed delay and known pulse signal
Pulse signal is provided.
2. external trigger pulsewidth prediction circuit according to claim 1 is it is characterised in that described pulse delay unit is to postpone
Buffer, DS1100-T chip or delay line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410654340.6A CN104485932B (en) | 2014-11-17 | 2014-11-17 | External trigger pulse width predicting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410654340.6A CN104485932B (en) | 2014-11-17 | 2014-11-17 | External trigger pulse width predicting circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104485932A CN104485932A (en) | 2015-04-01 |
| CN104485932B true CN104485932B (en) | 2017-02-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410654340.6A Expired - Fee Related CN104485932B (en) | 2014-11-17 | 2014-11-17 | External trigger pulse width predicting circuit |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004012279A (en) * | 2002-06-06 | 2004-01-15 | Mitsubishi Electric Corp | Pulse interval measurement circuit |
| CN1612478A (en) * | 2003-10-27 | 2005-05-04 | 扬智科技股份有限公司 | Automatic correcting device and method for pulse working period |
| CN101572551A (en) * | 2008-04-30 | 2009-11-04 | 中芯国际集成电路制造(北京)有限公司 | Time-to-digit converter and method thereof |
| CN101789774A (en) * | 2009-01-22 | 2010-07-28 | 中芯国际集成电路制造(上海)有限公司 | All-digital pulse width control circuit |
-
2014
- 2014-11-17 CN CN201410654340.6A patent/CN104485932B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004012279A (en) * | 2002-06-06 | 2004-01-15 | Mitsubishi Electric Corp | Pulse interval measurement circuit |
| CN1612478A (en) * | 2003-10-27 | 2005-05-04 | 扬智科技股份有限公司 | Automatic correcting device and method for pulse working period |
| CN101572551A (en) * | 2008-04-30 | 2009-11-04 | 中芯国际集成电路制造(北京)有限公司 | Time-to-digit converter and method thereof |
| CN101789774A (en) * | 2009-01-22 | 2010-07-28 | 中芯国际集成电路制造(上海)有限公司 | All-digital pulse width control circuit |
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| CN104485932A (en) | 2015-04-01 |
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Inventor after: Ji Shenghua Inventor after: Feng Jun Inventor after: Li Min Inventor after: Li Dehe Inventor after: Wang Jianqiang Inventor after: Shi Zhenguo Inventor after: Zhang Yongchen Inventor before: Li Dehe |
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