JPS6146642A - Reception data sampling pulse generating circuit for serial data transmitter - Google Patents

Abstract

PURPOSE:To attain ease of detection of a synchrorous word at the reception side and to prevent the deterioration of transmission efficiency of a data by generating a pulse sampling accurately a serial reception data at the center of each bit length at all times. CONSTITUTION:When a serial reception data is inputted to a terminal D1 of a D FF circuit 1a of a differentiation circuit 1, an output from a terminal Q1 is inputted to a terminal D2 of other D FF circuit 1b and an EXNOR 1c, and an output of the EXNOR 1c is inputted to a LOAD terminal of a hexadecimal counter 3. The hexadecimal counter 3 counts a reference clock inputted to the CLK terminal, the count is set to output terminals QA-QD, and when a preset start input is inputted to the LOAD terminal, a numeral inputted to preset input terminals A-D in this case is preset. An adder 6 inputs a sum of numerals inputted two sets of input terminals A1-A4, B1-B4 from output terminals SIGMA1-SIGMA4 to the preset input terminals A-D of the hexadecimal counter 3, and an RC signal is outputted from the counter 3 as the sampling pulse.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a cyclic, digital information transmission device (hereinafter referred to as O
NRZ (Nonr@turn to
In a serial data transmission device using a Z＠ro ) signal, in order to accurately sample the input data received as a serial binary signal code string, the input data is The present invention relates to a received data sampling pulse generation circuit for a serial data transmission device, which detects a synchronization deviation between a sampling pulse and a sampling pulse, corrects the deviation step by step, and always samples input data at the center thereof.

[Conventional technology]

When receiving serially transmitted data and converting it into parallelly transmitted data, it is customary to generate sampling pulses on the receiving side and sample the received data using these pulses. Figure 2 shows an overview of the conventional sampling method for serially received data, where the horizontal axis is the time axis and the received signal is shown in the figure ((
) is input as a serial binary code string in which the duration of 0 or 1 per bit is equal.

The sampling pulse is generated at a fixed period on the receiving side so as to be synchronized with the input signal, and the pulse width is extremely short compared to the duration of one bit of input data.
Ideally, it is perfectly synchronized with the input signal, and each pulse is located at the center (on the time axis) of each input data (FIG. 2 (b)). Figure 2 (C) shows the sampling data string extracted by the sampling pulse of Naka), whose information content is equal to that of the input data (in this case, 1,
0, 1.0...).

Figure 3 shows the main points of the frame synchronization method that has traditionally been used to maintain synchronization between serially received data and sampling pulses. A synchronization word with a specific pattern is placed at the beginning of the frame, followed by an information word 1 arranged in sequence.
．． S21S3. . On the receiving side, a pulse-like timing signal is generated every time a synchronization word arranged at a fixed periodic interval is detected in the transmission data (serial reception data), and the phase of the sampling pulse ((c) in the same figure) is determined by the timing signal. The reference is corrected and this phase relationship is maintained until the next frame's synchronization timing signal is generated again. In Fig. 3), as an example, the information word Φ2 is enlarged and the input data sequence is sampled by the sampling pulse of It can be seen that a sampling data sequence (1, 0, 1.1 in this case) with information content is obtained.

[Problem that the invention seeks to solve]

However, the following drawbacks have been pointed out in the past regarding this frame synchronization method.

(1) Synchronization correction of received data and sampling pulses is performed only when a synchronization word is received. Therefore, if the accuracy of the clock of the transmission data generation circuit on the transmission side (sending side) and the frequency of the sampling pulse on the receiving side is low, or if the number of information words in one frame is large, the deviation in 97 pre/g synchronization will gradually increase. There is a risk that

For the above reasons, extremely high frequency accuracy is required of the transmission data generating circuit on the transmitting side and the sampling pulse generating circuit on the receiving side, which tends to cause technical difficulties and economic disadvantages.

(2) Once the synchronization between the two is broken, J'L
Correct: = Since the P stage is missing, all received data until the next synchronization word is detected becomes error data.

Therefore, if the characteristics of the transmission line are poor (waveform distortion, level fluctuations, etc.) or if there is significant ambient noise, it becomes difficult to detect the synchronization word on the receiving side, resulting in a significant drop in data transmission efficiency.

[Means and operations for solving the problem] The present invention has been made in view of the above, and is designed to enable serially received data to always be sampled accurately at the center of each bit length.

On the receiving side, the standard clock pulse (
Generates a reference clock (hereinafter abbreviated as the reference clock), and detects the point in time at which a sampling pulse obtained by detecting the phase shift between the reference clock and the serial reception (detects the phase difference between the M data) is output at each ON10FF change point of the received data. The present invention provides a received data sampling pulse generation circuit for a serial data transmission device, which adjusts the reference clock period by one reference clock period in a direction that corrects the synchronization deviation.

Hereinafter, a received data sampling pulse generation circuit for a serial data transmission device according to the present invention will be explained in detail.

〔Example〕

FIG. 1 shows an embodiment of the present invention, in which serially received data is
N10 F At every F change point (in other words, every time the arrival of the leading edge of a data bit of 1 or 0 is sensed), a pulse (hereinafter referred to as reception (M
1 of the serially received data of the differentiating circuit 11 that generates the signal change point detection signal (hereinafter referred to as a signal change point detection signal), and a standard whose period is, for example, 1/16 (i.e., 1/16 T) of the T length (this duration is expressed as T). A reference clock generation circuit 2 that generates clock pulses, counts (divides) the reference clock pulses, and generates a ripple carrier signal (carry signal, hereinafter referred to as RO signal) at the same time as counting of all digits is completed 16 Decimal counter 3. An inverter (inverter) that performs a certain operation (details will be described later) on the constantly counted value of the hexadecimal counter 3 and sends it to the preset input terminal of the hexadecimal counter, which will be described later. 4, a NAND circuit (hereinafter referred to as NAND) 5 and an adder 6.

In addition, the differentiator circuit 1 includes two D-type flip-flops, and a flip-flop circuit 1.
a, 1b and an exclusive NOR circuit (hereinafter referred to as EXNOR) lc, ・D1*D1 and Ql,
Qs is an input terminal and an output terminal of these flip-flop circuits, respectively, and OLK is a clock terminal to which a reference clock is input. Serial reception data is D-type flip-flow.

The Qs terminal is input to the D1 terminal of another D-type flip-flop circuit 1b and E) G'JO.
Connected to one input terminal of R1e.

The output terminal Qs of the D-type 7 lip-flop circuit 1b is EXN.
Connected to the other input terminal of OR1c. The notice mentioned below,
E) Output of GJOR1e (output of differential circuit 1) is 1/1
The reception data change point detection signal with a time width of 6T is input to the LOAD terminal of the hexadecimal counter 3.

Hexadecimal counter 3 is the same OLK terminal (clock input terminal)
The reference clocks input to the output terminals QA, Q, , Qc, and Q are counted.

is set to In addition, the counter 3 has a preset function, and when the preset start input (in this case, the receptor data change point detection signal input from the differentiator circuit 1) is input to the LOAD terminal, the preset input terminal A , B
, O, and D are preset. In addition,
During the preset activation input, the hexadecimal counter 3 temporarily loses its counting function. Further, the RO signal output from the counter 3 functions as a sampling pulse for processing serially received data.

Adder 6 has 2411 input terminals A I + A 2
+ A ll5A4 and B1 r B2 # B9
*B4 and one set of output terminals Σ1, B2, B8
, B4. A1+ARM A! r A4 has hexadecimal counter output terminals Q, , Q, , Qc
, QDs are connected directly and in parallel. B1 e
Of B2 e B * m B4, BIB is connected to the output terminals QA, Qll-Qc, and Qn of the hexadecimal counter 3 via the inverter 4 or NAND 5, and % B8 a B4 is grounded.

Output terminals Σ1, B2, Σ1. Σ4 has input terminal A1
e A2 h 1g + A4 and B1 + B
The sum of the numbers input to l*B3 and B4 is output, and that number is sent to the preset input terminals A, B, and hexadecimal counter 3.
0. Input D as a parallel binary code string.

In the above configuration, the operation of the differentiating circuit 1 will be explained first. FIG. 4 is a timing chart illustrating the operation of each part of the circuit, in which (a) shows the serially received data (the input level of the D1 terminal of the flip-flop 1a), and (b) shows the flip-flop la.

The reference blocks (c) and 2) input to the OLK terminal of 1b are the output terminals of flip-flops la and Ib, Qs and Ib, respectively.
The output level of Qs (c) indicates the output level of FIXNOR1c. As shown in Figure 4 (a) and (b), the leading edge of the received data (the left edge of the figure in (a)) and the reference clock generally do not match in time, so Dl changes from L (0) to H. Even if it shifts to (1), Ql does not immediately shift to H,
When the next clock is input, it shifts to H ((c) in the same figure). Thereafter, the reference clock is input and as long as Dl remains high, the level of Ql remains high. Dl goes from H to L
When transitioning to , Ql does not immediately transition to L, but becomes L when the next reference clock is input (P right edge in the same figure)
. On the other hand, even if Ql (i.e., B2) transitions from L to H (left edge in Figure 3(C)), Ql does not immediately transition from L to H, and becomes H when the next reference clock is input. (right edge (as shown in the same figure)).

Similarly, Ql is delayed by one reference clock and H is fi.
Shift to L (right edge of the same figure (c)). Also, EX
Due to its nature, the NOR1c outputs fiH only when both of its input terminals are H or L, and outputs L when one of them is ■(, and the other is L).

As is clear from the fact that Ql and Q2 are connected to the input terminals of EXNOR1c, respectively, and from Figure 4 (C) and (2), the output of EXNOTL1c is connected in series as shown in Figure 4 (E). It shifts from H to L with a delay of (1/16 T) within the lock width from the ON10 FF change point of the received data, and returns to H after connecting this value for 1/16 T. This state in which EXNORlc temporarily becomes L is the above-mentioned received data change point detection signal.

(n) Next, the hexadecimal counter 3 counts the reference clock input to the OLK terminal, and the counted value is sent to the output terminals Q A, Q
B −Q c and Q n are set every moment, and further inputted to the input terminal of the adder 60 as a parallel binary code string. Next, another set of input terminals B! .

The numerical value manually input to Bm t Bl + B4 will be explained. 0, 1, 2, 3. ...The first decimal table of 14.15 is expressed in binary code in the first table. It is clear from this table that the count value of the hexadecimal counter is θ~7
In this case, the most significant digit of QA e Qs e QoeQD (
Q, ) is always 0 (input), so this value is inverted by the inverter 4 and input as 1 to the B2 terminal of the adder 6 and one of the input terminals of NAND B.
5, due to the nature of the circuit, outputs H only when all three input terminals are L, and always outputs L no matter what other combination of data is input. Therefore, in this case, the input of Bl (
The output of NAND 5) is always 0■, and since the input of Bs is lσ◇, the input terminal B
The number set in 1*B1 e Bl + B4 is 0010 in binary notation (2 in decimal notation). Therefore, the output terminals of adder 6 Σ凰 −Σ3 , Σ
8 and Σ4 output a value obtained by adding 2 to the count value of QA-QlltQc and QD, and input it to preset input terminals A, B, O, and D of the hexadecimal counter 3.

When the output of the hexadecimal counter 6 is 8 or 9, as is clear from Table 1, the highest digit QD is 1◇, the adder 60 input terminal B, and one of the NAND 50 input terminals. L
(0) is input. Further, in this case, since Q B -Q c are both 0■, all three input terminals of the NAND 5 are at L, and 1α◇ is input to the input terminal B of the adder 60. Therefore, input terminal B1 *B2 1B3 3
0001 (1 in decimal notation) is set in B4. Therefore, the output terminals Σ1, Σ2, Σ3 of the adder 6
, Σ4, the count value of the hexadecimal counter (QA, Q, .

The value obtained by adding 1 to the values of Qc and QD is output,
This value is the same for the same preset input terminals A, B, and O.

Enter in D. By similar consideration, when the count value of the hexadecimal counter 3 is 10 to 15, the adder 60 input terminal Bl
@ B21 Bs I The number to enter in B4 is oo
oo (all digits L) j5.Q of hexadecimal counter 3,,
The numerical values of Q, B, Qc, and QD are input as they are to the same preset input terminals A, B, O, and D. Interrelationship between the count value of hexadecimal counter 3, the preset input terminal, and the input/output terminal value of addition JI"Jr 6 ←"CC length indicator is N1
There are two tables.

Preset control input terminal r14 of hexadecimal counter 3) As long as LOAD is H, the same preset input terminals A and B
, O, D are all ignored, but the same T,
When a preset activation input (in this case, a reception data change point detection signal is input and this terminal temporarily becomes L) is input to the OAD terminal, the preset input terminals A and B are input at that point.

J) Hexadecimal counter 3 according to the data input to 0 and D
is preset, and the counting of the reference clock of the counter is then performed using this value as the super point.

It is clear from the above discussion that depending on the timing at which the hexadecimal counter 3 is preset (in other words, the timing at which the arrival of the beginning of each bit of received data is detected),
The hexadecimal counter 3 operates in the following manner.

(1) When preset when the count value is between θ and 7,
In this case, the hexadecimal counter 3 is preset to the value of "previous count + 2". This is because the increment by the normal reference clock is counted +l extra, and even if the normal counting is completed (count ul), the RO multiplied signal sampling pulse) is 16 times earlier by one reference clock. Numerous outputs are output from the decimal counter 3.

(2) If the count value is preset when it is 8 or 9, in this case hexadecimal counter 3 is "previous count value + 1"
is preset to the value of

For example, when the count value is preset to "8" and paddy, counting of all digits is completed after 7 reference clocks after the preset, and the RO multiplication signal is output from the hexadecimal counter 3.

(3) When the count value is preset when lθ~15, in this case, the hexadecimal counter 3 is preset to ``previous count value 10'', which is equivalent to omitting one normal step. Therefore, the completion of counting and the generation of the RO multiplication signal are delayed by one reference clock compared to the normal case.

Next, the function of correcting synchronization deviation by this circuit will be explained. Now, each received data (1 or 0) has arrived, and a received data change point detection signal is output from the differentiating circuit l, inputted to the LOAD terminal of the hexadecimal counter 3 as a preset start input, and the hexadecimal counter is preset. shall be taken as a thing. If the counted value at this time (the numerical value of the output terminals QAIQ, , Qc, QD) is "8", the counting is completed after 7 countings as described above, and the RO multiplied signal is output. Functions as a sampling pulse. Received data 1
The bit length corresponds to 16 reference clocks, and since the sampling pulse occurs 7 reference clocks after the leading edge of the data bit, the received data is sampled approximately at the center.

Next, as shown in FIG. 5(a), it is assumed that the data change point detection signal is detected when the count value of the hexadecimal counter 3 is 3-1.In this case, in the case of (1) above (counting box=1 to 7)", and the hexadecimal counter 3 is preset to "-5". The received data change point detection signal is detected between the third reference clock and the fourth reference clock, and when this signal is input to the LOAD terminal as a preset start input, (T, OAD ■,
During this period), as mentioned above, the hexadecimal counter 3 temporarily loses its counting function, so the fourth reference clock is not counted. Since the subsequent counting is performed starting from "5" preset in the counter, the counting is normally completed one clock earlier than usual, and the Re signal is output. In this case, compared to the state where both are synchronized, the received data is in a state where the received data is ahead (in other words, the reference clock is behind), and from this data change point detection, Re
The operation of shortening the time until the signal (sampling pulse) is output acts in the direction of correcting the delayed phase of the reference clock by one reference clock.

In addition, as shown in FIG. 5(b), when the data change point detection signal is detected when the count value of the hexadecimal counter 3 is 112'', in the case of (3) above (count value = 10 to 15 )
, and the hex counter 3 is preset to [-12J. The subsequent counting is performed starting from "12", and the counting is completed one reference clock later than in the normal case.
A Re signal is output. In this case, the phase relationship is such that the reference clock is advanced, so Re
The operation of delaying the time until the signal (sampling pulse) is output acts in the direction of correcting the leading phase of the reference clock pulse by one reference clock.

The above processing is performed for each received data change point, so
Initially, the sampling pulse and received data were asynchronous and 6. Even if the sampling pulse deviates from the center of the received data, one reference clock width (1/16
T) This is corrected by repeating this several times (even if the deviation between the two is maximum, repeating it eight times at most), the phase relationship between the two can be completely synchronized. Furthermore, in the -1 circuit, since the amount of phase correction for each point of change in the received data is small, there is an advantage that synchronization pull-in does not occur on average even when sijitter occurs due to distortion of the received data.

In this embodiment, the reference clock interval is set to 1/16 of 1 bit length, and a hexadecimal counter is used as a counter for dividing the reference clock. 1/2" (n is a positive integer), and the counter that divides the reference clock can be used as a 2n counter.Also, although we have explained the case where sampling is performed at the center of each received data, the calculation of the counter By changing the numerical value to be added to the numerical value, it is also possible to perform sampling at a desired position within the bit width of the received data.

〔Effect of the invention〕

As explained above, according to the received data sampling pulse generation circuit for a serial data transmission device of the present invention, a reference clock having a cycle of 1/2n (n is a positive integer) of 1 bit length of received data is generated on the receiving side. Then, at each ON10FF change point of the received data, the synchronization difference between the reference clock and the serially received data is detected, and the reference clock is changed by 1/1.
The time point at which the sampling pulse obtained by dividing the frequency by 2n is generated is set by 1 in the direction in which the synchronization difference is corrected.
Since the reference clock is adjusted one by one, the synchronization gap between the two is automatically corrected by repeating several times, and it is possible to always accurately sample the received data at the center of the 1-bit length of each received data after the fact. Now you can.

[Brief explanation of the drawing]

Figure 1: An explanatory diagram showing an embodiment of the present invention. Figure 2・
... A diagram illustrating an overview of a sampling method for serially received data. FIG. 3: A diagram explaining the principle of the conventional frame synchronization method. FIG. 4: A timing chart explaining the operation of the differentiating circuit. FIG. 5: A diagram illustrating the function of correcting synchronization deviation in this embodiment. Code table 1... Differential circuit, la, lb... Same type flip-flop circuit, lc... Same EXNOIt circuit, 2
・・・Reference clock generation circuit, 3... Hexadecimal counter, 4... Inverter, 5... 3-manpower NAN
D circuit, 6...adder.

Claims (1)

[Scope of Claims] A serial reception data sampling pulse generation circuit that generates a pulse for sampling serial reception data consisting of a binary code string of "1" and "0" having equal durations, comprising: 1 of the serial reception data. means for generating a reference clock pulse having a period of 1/2^n of a bit length; and means for determining the phase advance or lag between the reference clock pulse and the serially received data when the value of each bit of the serially received data changes. A serial data transmission device comprising: a means for detecting; and a means for adjusting the generation timing of the sampling pulse by a time corresponding to a predetermined number of pulses of the reference clock pulse according to the advance or lag of the phase. Receive data sampling pulse generation circuit.