JPH03123338U

JPH03123338U -

Info

Publication number: JPH03123338U
Application number: JP3258690U
Authority: JP
Priority date: 1990-03-27
Filing date: 1990-03-27
Publication date: 1991-12-16

Description

[Brief explanation of drawings]

第１図は本考案のデータ再生回路の一実施例を
示すブロツク図、第２図は本実施例における各信
号の時間関係を示すタイミングチヤート、第３図
は本実施例におけるカウント値１０５とロードカ
ウント値１０７との関係を示す図、第４図は従来
のデータ再生回路を示すブロツク図、第５図およ
び第６図は従来のデータ再生回路における各信号
の時間関係を示すタイミングチヤートである。１０，４０……タイミングパルス生成回路、１
１，４１……クロツク発生器、１２，４２……デ
ータ変化点検出器、１３，４３……タイミング発
生カウンタ、１４……カウント値モニタ部、１５
……ロードカウト値発生部、１６，４４……デー
タ再生フリツプフロツプ、１０１，１０４……受
信データ、１０２，４０２……クロツクパルス、
１０３，４０３……データ変化点パルス、１０４
，４０４……タイミングパルス、１０５……カウ
ント値、１０６……数値、１０７……ロードカウ
ント値、１０８，４０５……再生データ。 Fig. 1 is a block diagram showing one embodiment of the data reproducing circuit of the present invention, Fig. 2 is a timing chart showing the time relationship of each signal in this embodiment, and Fig. 3 is a count value 105 and load in this embodiment. FIG. 4 is a block diagram showing a conventional data reproducing circuit, and FIGS. 5 and 6 are timing charts showing the time relationship of each signal in the conventional data reproducing circuit. 10, 40...timing pulse generation circuit, 1
1, 41... Clock generator, 12, 42... Data change point detector, 13, 43... Timing generation counter, 14... Count value monitor section, 15
...Load count value generation unit, 16,44...Data reproducing flip-flop, 101,104...Received data, 102,402...Clock pulse,
103, 403...Data change point pulse, 104
,404...Timing pulse, 105...Count value, 106...Numeric value, 107...Load count value, 108,405...Reproduction data.

Claims

[Claims for Utility Model Registration] (1) In a timing pulse generation circuit that extracts a basic pulse repetition frequency component included in a pulse train of a received data signal and generates a timing pulse, the transmission speed of the received data signal is 2N times or a clock generator that outputs a clock pulse with a frequency of 2M×N times (M and N are natural numbers), which inputs the received data signal and the clock pulse, detects a data change point of the received data signal, and detects the change. a data change point detector that outputs a data change point pulse indicating the time of a point in synchronization with the clock pulse; and a data change point detector that inputs the clock pulse and the data change point pulse as an input clock signal and a load signal, respectively, The load count value is read as the initial value of the count value according to the count value, and the count value is counted up from the initial value in synchronization with the clock pulse, and the time for the count value to count up from 0 to 2N-1 is 1. A timing generation counter that outputs a timing pulse as a period and the count value in synchronization with the clock pulse, and a count value output from the timing generation counter are input, and the numerical value of the count value or the count value is set to 1. a load count value generator that outputs a value obtained by adding . (2) In the load count value generator, 1
The load count values for the count values of , 2, ..., N are 1, 2, ..., N, respectively, and N+1,
The load count values for the count values of N+2, ..., 2N-3 are N+3, N+4, ..., 2, respectively.
2. The timing pulse according to claim 1, wherein the load count value for a count value of 2N-2 is 0, and the load count value for a count value of 0, 2N-1 is 1. generation circuit. (3) In a data regeneration circuit that samples a received data signal with a timing pulse and restores the pulse waveform of the received data signal to its original shape that has been corrupted due to attenuation or distortion during transmission, means for generating the timing pulse is claimed. 3. A data reproducing circuit comprising the timing pulse generating circuit according to item 1 or 2.