JPS58164336U

JPS58164336U - Pulse train conversion circuit

Info

Publication number: JPS58164336U
Application number: JP5444381U
Authority: JP
Inventors: 茂細田
Original assignee: 株式会社日立製作所
Priority date: 1981-04-17
Filing date: 1981-04-17
Publication date: 1983-11-01

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は従来のパルス−列変換回路の一例を示すブロッ
ク図、第２図ａ−ｇは第１図の回路における各部のタイ
ムチャート、第３図は、本考案のパルス列変換回路の実
施例のブロック図、第４図ｈ〜ｍは第３図の回路におけ
る各部のタイムチャートである。４．１７・・・分周回路、５，２０・・・クロック合成
回路、７，８，２１．２２−ｎＸＮビットシフトレジス
タ、９，１０．１９・・・１ビツトシフトレジスタ、１
１．　１２．　２３．　２４・・・ゲート素子、３゜２
５・・・ＯＲ（論理和）素子。：）Ｆ　３　凪第４国FIG. 1 is a block diagram showing an example of a conventional pulse train conversion circuit, FIGS. 2 a to 2 g are time charts of various parts of the circuit in FIG. 1, and FIG. 3 is an embodiment of the pulse train conversion circuit of the present invention. The block diagram of FIG. 4, h to m, is a time chart of each part in the circuit of FIG. 4.17... Frequency divider circuit, 5, 20... Clock synthesis circuit, 7, 8, 21.22-nXN bit shift register, 9, 10.19... 1 bit shift register, 1
1. 12. 23. 24...Gate element, 3゜2
5...OR (logical sum) element. :) F 3 Nagi 4th country

Claims

[Scope of utility model registration request]

A frequency divider circuit that stores nxN burst signals of N pulse trains in an nxN bit shift register, divides the basic clock, and synthesizes the clock to be added to the shift register to output the nxN signals.Clock synthesis The basic circuit is a gate signal generation circuit that generates the gate signal necessary to obtain a burst signal of nxN pulse trains by passing the output of the shift register through a gate element, and a clock that operates the shift register in response to the gate signal. a shift register circuit that delays one clock cycle;
It is composed of an AND (logical product) element, an OR (logical sum) element, etc., and synthesizes the lock applied to the shift register using a clock delayed by one period of the basic clock with respect to the gate signal, and generates a burst signal of N pulse trains. nxN
What is claimed is: 1. A pulse train conversion circuit comprising: converting the signal into a signal of nxN pulse trains, and adding a gate element to the gate signal to obtain a burst signal of nxN pulse trains.