JPH0467826U

JPH0467826U -

Info

Publication number: JPH0467826U
Application number: JP11098390U
Authority: JP
Priority date: 1990-10-23
Filing date: 1990-10-23
Publication date: 1992-06-16

Description

[Brief explanation of drawings]

第１図は本考案の一実施例を示すブロツク図、
第２図はその動作を示すタイミングチヤート、第
３図はパラレル・データ／シリアル・データ変換
回路の従来例を示すブロツク図、第４図はその動
作を示すタイミングチヤートである。１−１〜１−３，１１−１〜１１−３……分周
回路、２，１４−１〜１４−６，１９……論理和
回路、３−１〜３−６……選択回路、４−１，４
−６……バツフア回路、１３−１〜１３−６……
入力バツフア回路、２０……出力バツフア回路。 FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a timing chart showing its operation, FIG. 3 is a block diagram showing a conventional example of a parallel data/serial data conversion circuit, and FIG. 4 is a timing chart showing its operation. 1-1 to 1-3, 11-1 to 11-3... frequency divider circuit, 2, 14-1 to 14-6, 19... logical sum circuit, 3-1 to 3-6... selection circuit, 4-1, 4
-6... Buffer circuit, 13-1 to 13-6...
Input buffer circuit, 20...output buffer circuit.

Claims

[Scope of utility model registration request]

Parallel data/serial converter that converts input parallel data to serial data and outputs it.
In the data conversion circuit, means for converting the continuous parallel data into single-shot data using a data selection signal generated from a basic clock signal at a predetermined frequency division ratio, and means for latching the single-shot data with the basic clock signal; A parallel data/serial device characterized in that the latched single-shot data is shifted by a predetermined clock amount at the timing of the basic clock signal using the data selection signal, and synthesized and concatenated to generate serial data.・Data conversion circuit.