JPH02123629U - - Google Patents
Info
- Publication number
- JPH02123629U JPH02123629U JP3281589U JP3281589U JPH02123629U JP H02123629 U JPH02123629 U JP H02123629U JP 3281589 U JP3281589 U JP 3281589U JP 3281589 U JP3281589 U JP 3281589U JP H02123629 U JPH02123629 U JP H02123629U
- Authority
- JP
- Japan
- Prior art keywords
- clock signal
- data rate
- section
- buffer memory
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000007493 shaping process Methods 0.000 claims description 2
- 238000012544 monitoring process Methods 0.000 claims 1
- 230000004044 response Effects 0.000 claims 1
- 230000000630 rising effect Effects 0.000 claims 1
- 238000013500 data storage Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
Description
第１図はこの考案の一実施例を示す機能図、第
２図は従来のデジタル信号入力装置の機能図であ
る。
図において、１は波形整形部、２はデータ記憶
・出力部、３はモノパルス発生部、４はデータ記
憶部、５はデータ出力部、６はデータレート制御
部である。なお、各図中同一符号は同一又は相当
部分を示す。
FIG. 1 is a functional diagram showing an embodiment of this invention, and FIG. 2 is a functional diagram of a conventional digital signal input device. In the figure, 1 is a waveform shaping section, 2 is a data storage/output section, 3 is a monopulse generation section, 4 is a data storage section, 5 is a data output section, and 6 is a data rate control section. Note that the same reference numerals in each figure indicate the same or equivalent parts.
Claims (1)
び立下り部分を急峻にし、雑音を除去するための
波形整形部と、波形整形されたクロツク信号を固
定パルス幅のクロツク信号に変換するためのモノ
パルス発生部と、モノパレス発生部からのクロツ
ク信号に同期してデータを一度記憶するバツフア
メモリ部と、入力させる機器からの入力要求クロ
ツク信号によりデータをバツフアメモリ部から読
み出して出力するデータ出力部と、バツフアメモ
リ部の記憶可能量をモニタし、記憶可能量に応じ
て入力されるデジタル信号のデータ速度を制御す
るためのデータレート制御部を備え、速いデータ
レートを有するデジタル信号を連続して入力でき
ることを特徴とするデジタル信号入力装置。 a waveform shaping section for sharpening the rising and falling portions of digital signals and clock signals to remove noise; and a monopulse generating section for converting the waveform-shaped clock signal into a clock signal with a fixed pulse width. A buffer memory section that stores data once in synchronization with the clock signal from the monopare generator, a data output section that reads and outputs data from the buffer memory section in response to an input request clock signal from the input device, and a storage capacity of the buffer memory section. A digital signal input device comprising a data rate control unit for monitoring the data rate and controlling the data rate of the input digital signal according to the storage capacity, and capable of continuously inputting digital signals having a high data rate. Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3281589U JPH02123629U (en) | 1989-03-23 | 1989-03-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3281589U JPH02123629U (en) | 1989-03-23 | 1989-03-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02123629U true JPH02123629U (en) | 1990-10-11 |
Family
ID=31259397
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3281589U Pending JPH02123629U (en) | 1989-03-23 | 1989-03-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02123629U (en) |
-
1989
- 1989-03-23 JP JP3281589U patent/JPH02123629U/ja active Pending