JPH01155550U - - Google Patents

Info

Publication number
JPH01155550U
JPH01155550U JP5050888U JP5050888U JPH01155550U JP H01155550 U JPH01155550 U JP H01155550U JP 5050888 U JP5050888 U JP 5050888U JP 5050888 U JP5050888 U JP 5050888U JP H01155550 U JPH01155550 U JP H01155550U
Authority
JP
Japan
Prior art keywords
serial
parallel
signal line
data
shift clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5050888U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5050888U priority Critical patent/JPH01155550U/ja
Publication of JPH01155550U publication Critical patent/JPH01155550U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の実施例を示すブロツク図、
第2図は従来のバス拡張装置を示すブロツク図で
ある。
Figure 1 is a block diagram showing an embodiment of this invention.
FIG. 2 is a block diagram showing a conventional bus expansion device.

Claims (1)

【実用新案登録請求の範囲】 外部ユニツトに対する命令ごとにストローブを
発生するストローブ発生器と、 そのストローブによつてシフトクロツクを発生
するシフトクロツク発生器と、 そのシフトクロツクによつてCPUのバスデー
タをパラレルシリアル変換する並列直列変換器と
、 その並列直列変換器よりのシリアルデータを伝
送するデータ信号線と、 上記シフトクロツクを伝送するクロツク信号線
と、 外部ユニツトに設けられ、上記データ信号線か
らのシリアルデータを上記クロツク信号線からの
シフトクロツクによりシリアルパラレル変換する
直列並列変換器と、 その直列並列変換器の出力側に接続された外部
バスとを具備するバス拡張装置。
[Claims for Utility Model Registration] A strobe generator that generates a strobe for each command to an external unit, a shift clock generator that generates a shift clock using the strobe, and parallel-to-serial conversion of CPU bus data using the shift clock. a parallel-to-serial converter, a data signal line to transmit serial data from the parallel-to-serial converter, a clock signal line to transmit the shift clock, and a clock signal line to transmit the serial data from the data signal line to the external unit. A bus expansion device comprising a serial-to-parallel converter that performs serial-to-parallel conversion using a shift clock from a clock signal line, and an external bus connected to the output side of the serial-to-parallel converter.
JP5050888U 1988-04-15 1988-04-15 Pending JPH01155550U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5050888U JPH01155550U (en) 1988-04-15 1988-04-15

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5050888U JPH01155550U (en) 1988-04-15 1988-04-15

Publications (1)

Publication Number Publication Date
JPH01155550U true JPH01155550U (en) 1989-10-25

Family

ID=31276554

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5050888U Pending JPH01155550U (en) 1988-04-15 1988-04-15

Country Status (1)

Country Link
JP (1) JPH01155550U (en)

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