JPS63175252U - - Google Patents

Description

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a timing chart of Fig. 1, Fig. 3 is a diagram showing a conventional serial data input/output device, and Fig. 4 is a timing chart of Fig. 3. It's a chat. In the figure, 1 is an output side device, 2 is a computer, 3 is a register, 4 is a P/S converter, 5 is an input side device,
6 is an S/P converter, 7 is a timing controller, 8 is a computer, 9 is a clock generator, 10 is a star bit detection circuit, and 11 is a clock generator. In addition, the same or equivalent parts in the figures are indicated by the same reference numerals.

Claims (1)

[Scope of utility model registration request] an output side device consisting of a computer that outputs data in parallel, a register that latches and outputs the output of the computer, and a parallel-to-serial converter that inputs the output of the register and converts it into serial data; Parallel of side equipment
A serial-parallel converter that inputs the output of the serial converter and converts it to parallel data, inputs the data from the serial-parallel converter mentioned above,
A computer that constitutes the output side device, a computer that outputs a data update signal to the register, a computer that inputs the frequency setting signal and a transfer start signal from the computer, and a parallel converter that constitutes the serial-to-parallel converter and the output side device. 1. A serial data input/output device comprising an input side device constituted by a timing controller that outputs a transfer clock to the serial converter and outputs a transfer end signal to the computer.