JPS61196345U - - Google Patents
Info
- Publication number
- JPS61196345U JPS61196345U JP8149085U JP8149085U JPS61196345U JP S61196345 U JPS61196345 U JP S61196345U JP 8149085 U JP8149085 U JP 8149085U JP 8149085 U JP8149085 U JP 8149085U JP S61196345 U JPS61196345 U JP S61196345U
- Authority
- JP
- Japan
- Prior art keywords
- diagnostic
- circuit
- digital
- data
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000010354 integration Effects 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Description
第１図は本願の一実施例のブロツク図、第２図
は本願の他の実施例のブロツク図である。
１０：外部入力データ、１２：診断用データ、
１４：外部入力クロツク、１６：診断用クロツク
ＯＮ／ＯＦＦ信号、１８：デイジタル積算回路、
１０４，２０４：診断用データ・レジスタ、１０
８，２０８：診断用クロツク発生器。
FIG. 1 is a block diagram of one embodiment of the present application, and FIG. 2 is a block diagram of another embodiment of the present application. 10: External input data, 12: Diagnostic data,
14: External input clock, 16: Diagnostic clock ON/OFF signal, 18: Digital integration circuit,
104, 204: Diagnostic data register, 10
8,208: Diagnostic clock generator.
Claims (1)
して積算するデイジタル積算回路と、 診断用デイジタル、データを保持する診断デー
タ回路と、 診断用クロツク発生回路と を設け、制御信号に応答して外部入力デイジタル
・データ及び外部入力クロツクまたは前記診断デ
ータ回路中の診断用デイジタル・データ及び前記
診断用クロツク発生回路からの診断用クロツクの
一方の組を前記入力デイジタル・データ及び入力
クロツクとして前記デイジタル積算回路に積算動
作を行なわしめるデイジタル積算装置。[Scope of Claim for Utility Model Registration] A digital integration circuit that integrates input digital data in response to an input clock, a diagnostic data circuit that holds diagnostic digital data, and a diagnostic clock generation circuit that generates control signals. in response to one set of external input digital data and an external input clock or diagnostic digital data in the diagnostic data circuit and a diagnostic clock from the diagnostic clock generation circuit. A digital integration device that causes the digital integration circuit to perform an integration operation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8149085U JPH0325229Y2 (en) | 1985-05-30 | 1985-05-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8149085U JPH0325229Y2 (en) | 1985-05-30 | 1985-05-30 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61196345U true JPS61196345U (en) | 1986-12-08 |
| JPH0325229Y2 JPH0325229Y2 (en) | 1991-05-31 |
Family
ID=30628320
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8149085U Expired JPH0325229Y2 (en) | 1985-05-30 | 1985-05-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0325229Y2 (en) |
-
1985
- 1985-05-30 JP JP8149085U patent/JPH0325229Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0325229Y2 (en) | 1991-05-31 |
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