JPS61168446U - - Google Patents

Info

Publication number
JPS61168446U
JPS61168446U JP4759685U JP4759685U JPS61168446U JP S61168446 U JPS61168446 U JP S61168446U JP 4759685 U JP4759685 U JP 4759685U JP 4759685 U JP4759685 U JP 4759685U JP S61168446 U JPS61168446 U JP S61168446U
Authority
JP
Japan
Prior art keywords
circuit
bus line
buffer circuit
power consumption
low power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4759685U
Other languages
Japanese (ja)
Other versions
JPH04440Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP4759685U priority Critical patent/JPH04440Y2/ja
Publication of JPS61168446U publication Critical patent/JPS61168446U/ja
Application granted granted Critical
Publication of JPH04440Y2 publication Critical patent/JPH04440Y2/ja
Expired legal-status Critical Current

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  • Logic Circuits (AREA)
  • Dc Digital Transmission (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、バス・ラインの一部を示す回路図で
ある。第2図は、そのタイミングチヤートである
。 「符号の説明」、1……3Sバツフア回路、2
……バス・ライン、3……抵抗器、4,5……バ
ツフア回路、6……インバータ回路、7……EX
OR回路。
FIG. 1 is a circuit diagram showing part of a bus line. FIG. 2 is the timing chart. "Explanation of symbols", 1...3S buffer circuit, 2
...Bus line, 3...Resistor, 4, 5...Buffer circuit, 6...Inverter circuit, 7...EX
OR circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] CMOS IC等の低消費電力素子を使用した
コンピユータのバス・ラインのターミネート回路
に於いて、前記バス・ラインに接続されたバツフ
ア回路と、前記バツフア回路の入出力間に接続さ
れた抵抗器とから成るバス・ラインのターミネー
ト回路。
In a computer bus line termination circuit using low power consumption devices such as CMOS ICs, there is a buffer circuit connected to the bus line and a resistor connected between the input and output of the buffer circuit. Terminating circuit for bus lines.
JP4759685U 1985-04-03 1985-04-03 Expired JPH04440Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4759685U JPH04440Y2 (en) 1985-04-03 1985-04-03

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4759685U JPH04440Y2 (en) 1985-04-03 1985-04-03

Publications (2)

Publication Number Publication Date
JPS61168446U true JPS61168446U (en) 1986-10-18
JPH04440Y2 JPH04440Y2 (en) 1992-01-08

Family

ID=30563071

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4759685U Expired JPH04440Y2 (en) 1985-04-03 1985-04-03

Country Status (1)

Country Link
JP (1) JPH04440Y2 (en)

Also Published As

Publication number Publication date
JPH04440Y2 (en) 1992-01-08

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