JPH01154482U - - Google Patents
Info
- Publication number
- JPH01154482U JPH01154482U JP5058688U JP5058688U JPH01154482U JP H01154482 U JPH01154482 U JP H01154482U JP 5058688 U JP5058688 U JP 5058688U JP 5058688 U JP5058688 U JP 5058688U JP H01154482 U JPH01154482 U JP H01154482U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- control section
- pseudo error
- error input
- signal line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Logic Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
第１図は本考案の一実施例の回路図、第２図は
同実施例のタイミングチヤート、第３図はＥＣＬ
のＯＲ、ＮＯＲゲートの回路図である。
図において、１は第１のトランジスタ、２は第
２のトランジスタ、３は擬似エラー入力信号線、
５は制御部である。なお、図中、同一符号は、同
一又は相当部分を示す。
Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a timing chart of the same embodiment, and Fig. 3 is an ECL
FIG. 2 is a circuit diagram of an OR gate and a NOR gate. In the figure, 1 is a first transistor, 2 is a second transistor, 3 is a pseudo error input signal line,
5 is a control section. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
タと第２のトランジスタの直列接続体と、第１の
トランジスタと第２のトランジスタの共通接続点
に接続された擬似エラー入力信号線と、第１のト
ランジスタ、第２のトランジスタの各入力に接続
された制御部とを備え、かつ該制御部は、第１の
トランジスタ、第２のトランジスタが共にオフ、
第１のトランジスタがオンで第２のトランジスタ
がオフ、ごく短期間第１のトランジスタがオフで
第２のトランジスタがオンの三態様で第１のトラ
ンジスタ、第２のトランジスタの制御ができるも
のであることを特徴とするＥＣＬ回路の擬似エラ
ー入力装置。 a series connection body of a first transistor and a second transistor connected between ground and a negative power supply; a pseudo error input signal line connected to a common connection point of the first transistor and the second transistor; and a control section connected to each input of the transistor and the second transistor, and the control section is configured to turn off both the first transistor and the second transistor.
The first transistor and the second transistor can be controlled in three ways: the first transistor is on and the second transistor is off, and the first transistor is off and the second transistor is on for a very short period of time. A pseudo error input device for an ECL circuit, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5058688U JPH01154482U (en) | 1988-04-15 | 1988-04-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5058688U JPH01154482U (en) | 1988-04-15 | 1988-04-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01154482U true JPH01154482U (en) | 1989-10-24 |
Family
ID=31276624
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5058688U Pending JPH01154482U (en) | 1988-04-15 | 1988-04-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01154482U (en) |
-
1988
- 1988-04-15 JP JP5058688U patent/JPH01154482U/ja active Pending