JPH01154483U - - Google Patents
Info
- Publication number
- JPH01154483U JPH01154483U JP5058788U JP5058788U JPH01154483U JP H01154483 U JPH01154483 U JP H01154483U JP 5058788 U JP5058788 U JP 5058788U JP 5058788 U JP5058788 U JP 5058788U JP H01154483 U JPH01154483 U JP H01154483U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- control section
- pseudo
- input side
- error input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Description
第１図は本考案の一実施例の回路図、第２図は
同実施例のタイミングチヤート、第３図はＴＴＬ
のＮＡＮＤゲートの回路図である。
図において、１は第１のトランジスタ、２は第
２のトランジスタ、３は擬似エラー入力信号線、
５は制御部である。
Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a timing chart of the same embodiment, and Fig. 3 is a TTL
FIG. 2 is a circuit diagram of a NAND gate. In the figure, 1 is a first transistor, 2 is a second transistor, 3 is a pseudo error input signal line,
5 is a control section.
Claims (1)
タと第２のトランジスタの直列接続体と、第１の
トランジスタと第２のトランジスタの共通接続点
に接続された擬似エラー入力信号線と、第１のト
ランジスタ、第２のトランジスタの各入力側に接
続された制御部とを備え、かつ該制御部は、第１
のトランジスタ、第２のトランジスタが共にオフ
、ごく短期間第１のトランジスタがオンで第２の
トランジスタがオフ、第１のトランジスタがオフ
で第２のトランジスタがオンの三態様で第１のト
ランジスタ、第２のトランジスタの制御ができる
ものであることを特徴とするＴＴＬ回路の擬似エ
ラー入力装置。 a series connection body of a first transistor and a second transistor connected between a positive power supply and ground; a pseudo error input signal line connected to a common connection point of the first transistor and the second transistor; a transistor, and a control section connected to each input side of the second transistor, and the control section is connected to each input side of the first transistor.
the first transistor in three modes: both transistors are off, the second transistor is off, the first transistor is on and the second transistor is off for a very short period of time, and the first transistor is off and the second transistor is on; A pseudo-error input device for a TTL circuit, characterized in that it is capable of controlling a second transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5058788U JPH01154483U (en) | 1988-04-15 | 1988-04-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5058788U JPH01154483U (en) | 1988-04-15 | 1988-04-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01154483U true JPH01154483U (en) | 1989-10-24 |
Family
ID=31276625
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5058788U Pending JPH01154483U (en) | 1988-04-15 | 1988-04-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01154483U (en) |
-
1988
- 1988-04-15 JP JP5058788U patent/JPH01154483U/ja active Pending