JPS6434836U

JPS6434836U -

Info

Publication number: JPS6434836U
Application number: JP12708387U
Authority: JP
Priority date: 1987-08-21
Filing date: 1987-08-21
Publication date: 1989-03-03

Description

[Brief explanation of the drawing]

第１図は、この考案の電源オフデイレイタイマ
回路を使用する電源回路の一例を示すブロツク図
、第２図は上記電源オフデイレイタイマ回路の論
理回路図、第３図Ａは上記電源オフデイレイタイ
マ回路の各部の信号のタイミングチヤート、同図
Ｂは上記電源オフデイレイタイマ回路に使用する
論理ゲートの真理値表である。１……接続部、２……ＮＦＢ、３，８……整流
回路、４……インバータ回路、５……インバータ
制御回路、６……電源オフデイレイタイマ回路、
７……冷却フアン、９……負荷、１０，１１……
ＡＮＤゲート、１２……ＯＲゲート。 Fig. 1 is a block diagram showing an example of a power supply circuit using the power off delay timer circuit of this invention, Fig. 2 is a logic circuit diagram of the above power off delay timer circuit, and Fig. 3A is a block diagram of the above power off delay timer circuit. The timing chart of the signals in each part of the circuit is shown in FIG. 1... Connection section, 2... NFB, 3, 8... Rectifier circuit, 4... Inverter circuit, 5... Inverter control circuit, 6... Power off delay timer circuit,
7...Cooling fan, 9...Load, 10, 11...
AND gate, 12...OR gate.

補正昭６２．１２．２図面の簡単な説明を次のように補正する。明細書第７頁第１６行ないし第１９行の「第３
図Ａは……同図Ｂは……である。」の記載を「第
３図は、上記電源オフデイレイタイマ回路の各部
の信号タイミング波形とその回路に使用する論理
ゲートの真理値を示す図である。」に補正する。Amendment December 2, 1982 The brief description of the drawing is amended as follows. “No. 3” on page 7, line 16 to line 19 of the specification
Figure A is... Figure B is... '' has been corrected to ``Figure 3 is a diagram showing the signal timing waveforms of each part of the power-off delay timer circuit and the truth values of the logic gates used in the circuit.''

Claims

[Scope of utility model registration request]

A commercial AC power source, an electrical device that supplies power to a load via a connection section and a main switch that turn on and off the power source, a cooling fan that cools the load or the electrical device, and a cooling fan that supplies power to the load. In the power-off delay timer circuit, which stops the operation of the cooling fan after stopping the power supply, the cooling fan continues to operate for a predetermined period of time, and then the cooling fan stops operating. , a signal for determining the on/off state of the main on/off switch, and a signal for determining the timer integrated circuit that starts from the off state of the main on/off switch and turns off after a certain period of time has elapsed. A power-off delay timer circuit characterized in that the operation of the cooling fan is controlled by the output of a logic circuit inputted with the power-off delay timer circuit.