JPH03104244U - - Google Patents
Info
- Publication number
- JPH03104244U JPH03104244U JP1129190U JP1129190U JPH03104244U JP H03104244 U JPH03104244 U JP H03104244U JP 1129190 U JP1129190 U JP 1129190U JP 1129190 U JP1129190 U JP 1129190U JP H03104244 U JPH03104244 U JP H03104244U
- Authority
- JP
- Japan
- Prior art keywords
- input
- output
- controls
- output port
- port
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
Description
第１図は本考案の第１の実施例を説明するため
の回路構成図、第２図は第１図における入出力状
態を示す図、第３図は本考案の第２の実施例を説
明するための回路構成図、第４図は第３図におけ
る入出力状態を示す図、第５図は従来例を説明す
るための回路図である。
１……ＮＡＮＤゲート、２……ＮＯＲゲート、
３……出力バツフア、４……インバータ、５……
出力ラツチ、６……ラツチ、６ａ〜６ｄ……入出
力切り換えレジスタ、７……Ｐチヤンネルのトラ
ンジスタ、８……Ｎチヤンネルのトランジスタ、
９ａ〜９ｈ……入出力端子、１０……内部バス、
１１……電源。
Figure 1 is a circuit configuration diagram for explaining the first embodiment of the present invention, Figure 2 is a diagram showing the input/output state in Figure 1, and Figure 3 is for explaining the second embodiment of the present invention. FIG. 4 is a diagram showing the input/output state in FIG. 3, and FIG. 5 is a circuit diagram for explaining a conventional example. 1...NAND gate, 2...NOR gate,
3... Output buffer, 4... Inverter, 5...
Output latch, 6... Latch, 6a to 6d... Input/output switching register, 7... P channel transistor, 8... N channel transistor,
9a to 9h...Input/output terminal, 10...Internal bus,
11...Power supply.
Claims (1)
るか出力ポートとするかを制御する入出力ポート
制御回路において、少なくとも１本の前記入出力
ポートの入出力状態設定を制御する第１の入出力
切り換え用レジスタと、複数本の前記入出力ポー
トの入出力設定を同時に制御する第２の入出力切
り換え用レジスタとを有することを特徴とする入
出力ポート制御回路。 In an input/output port control circuit that controls whether each of a plurality of input/output ports is used as an input port or an output port, a first input/output switching circuit that controls the input/output state setting of at least one input/output port. An input/output port control circuit comprising a register and a second input/output switching register that simultaneously controls input/output settings of a plurality of input/output ports.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1129190U JPH03104244U (en) | 1990-02-06 | 1990-02-06 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1129190U JPH03104244U (en) | 1990-02-06 | 1990-02-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03104244U true JPH03104244U (en) | 1991-10-29 |
Family
ID=31514824
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1129190U Pending JPH03104244U (en) | 1990-02-06 | 1990-02-06 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03104244U (en) |
-
1990
- 1990-02-06 JP JP1129190U patent/JPH03104244U/ja active Pending
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