JPS62147047U - - Google Patents

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Publication number
JPS62147047U
JPS62147047U JP3278686U JP3278686U JPS62147047U JP S62147047 U JPS62147047 U JP S62147047U JP 3278686 U JP3278686 U JP 3278686U JP 3278686 U JP3278686 U JP 3278686U JP S62147047 U JPS62147047 U JP S62147047U
Authority
JP
Japan
Prior art keywords
elapsed
predetermined time
control signal
delay gate
gate circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3278686U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3278686U priority Critical patent/JPS62147047U/ja
Publication of JPS62147047U publication Critical patent/JPS62147047U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示すブロツク図、
第2図は第1図の実施例の遅延ゲート回路の一例
を示す回路図である。 1…遅延ゲート回路、2…バスドライバ回路、
3…バスライン、11…ゲート回路、12…遅延
回路、C…コンデンサ、D…定電圧ダイオー
ド、D…ダイオード、Q…NAND回路、R
,R…抵抗。
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a circuit diagram showing an example of the delay gate circuit of the embodiment shown in FIG. 1... Delay gate circuit, 2... Bus driver circuit,
3... Bus line, 11... Gate circuit, 12... Delay circuit, C 1 ... Capacitor, D 1 ... Constant voltage diode, D 2 ... Diode, Q 1 ... NAND circuit, R
1 , R2 ...resistance.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 電源投入時から所定時間経過するまでは非能動
状態の制御信号を出力し、前記所定時間経過後は
制御部からの制御信号を伝達する遅延ゲート回路
と、この遅延ゲート回路からの制御信号によりバ
スラインへのデータの伝達を制御するバスドライ
バ回路とを有することを特徴とするバス接続回路
A delay gate circuit outputs a control signal in an inactive state until a predetermined time has elapsed since the power is turned on, and after the predetermined time has elapsed, a delay gate circuit transmits a control signal from the control section. A bus connection circuit comprising: a bus driver circuit that controls transmission of data to a line.
JP3278686U 1986-03-07 1986-03-07 Pending JPS62147047U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3278686U JPS62147047U (en) 1986-03-07 1986-03-07

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3278686U JPS62147047U (en) 1986-03-07 1986-03-07

Publications (1)

Publication Number Publication Date
JPS62147047U true JPS62147047U (en) 1987-09-17

Family

ID=30839795

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3278686U Pending JPS62147047U (en) 1986-03-07 1986-03-07

Country Status (1)

Country Link
JP (1) JPS62147047U (en)

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