JPS63107052U - - Google Patents
Info
- Publication number
- JPS63107052U JPS63107052U JP20188686U JP20188686U JPS63107052U JP S63107052 U JPS63107052 U JP S63107052U JP 20188686 U JP20188686 U JP 20188686U JP 20188686 U JP20188686 U JP 20188686U JP S63107052 U JPS63107052 U JP S63107052U
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- port
- input
- microcomputer
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Microcomputers (AREA)
- Information Transfer Systems (AREA)
Description
第１図は本考案の一実施例の構成を示すブロツ
ク図、第２図は第１図におけるＡ部分を詳細に説
明する回路図、第３図は第２図におけるＦＥＴの
状態とＤＩＰＳＷの状態および入出力信号との対
応関係を示す図、第４図は従来の回路モジユール
の構成を示すブロツク図である。
１，６……マイコン、２……入力ポート、３…
…出力ポート、４，１２……ＤＩＰＳＷ、５，７
……動作回路、８……データ設定回路、９……入
出力兼用ポート、１０……プルアツプ抵抗、１１
……プルダウン抵抗、Ｑ１，Ｑ２，Ｑ３……ＦＥ
Ｔ。
Fig. 1 is a block diagram showing the configuration of an embodiment of the present invention, Fig. 2 is a circuit diagram explaining in detail the part A in Fig. 1, and Fig. 3 is the state of the FET and the state of the DIPSW in Fig. 2. FIG. 4 is a block diagram showing the configuration of a conventional circuit module. 1, 6...Microcomputer, 2...Input port, 3...
...Output port, 4, 12...DIPSW, 5, 7
...Operating circuit, 8...Data setting circuit, 9...I/O port, 10...Pull-up resistor, 11
...Pull-down resistor, Q 1 , Q 2 , Q 3 ...FE
T.
Claims (1)
出力端子に接続された入出力兼用ポートと、この
ポートの他方の端子と他の動作回路とを接続する
ラインをグランドレベルと電源レベルとのいずれ
かに接続するスイツチとを備えてなることを特徴
とする回路モジユール。 Connect the input/output port, one terminal of which is connected to the data input/output terminal of the microcomputer, and the line that connects the other terminal of this port to other operating circuits to either the ground level or the power supply level. A circuit module characterized by comprising a switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20188686U JPS63107052U (en) | 1986-12-29 | 1986-12-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20188686U JPS63107052U (en) | 1986-12-29 | 1986-12-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63107052U true JPS63107052U (en) | 1988-07-11 |
Family
ID=31165761
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20188686U Pending JPS63107052U (en) | 1986-12-29 | 1986-12-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63107052U (en) |
-
1986
- 1986-12-29 JP JP20188686U patent/JPS63107052U/ja active Pending
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