JPS639632U - - Google Patents
Info
- Publication number
- JPS639632U JPS639632U JP10056786U JP10056786U JPS639632U JP S639632 U JPS639632 U JP S639632U JP 10056786 U JP10056786 U JP 10056786U JP 10056786 U JP10056786 U JP 10056786U JP S639632 U JPS639632 U JP S639632U
- Authority
- JP
- Japan
- Prior art keywords
- signal line
- level
- switching element
- microcomputer system
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000004913 activation Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Bus Control (AREA)
Description
第１図はこの考案にかかるコンピユータシステ
ムを示す回路図、第２図は従来のコンピユータシ
ステムのブロツク接続図である。
１１はマイクロプロセツサ、１３はデコーダ、
１４は信号線、１５はスイツチング素子、２０は
トランジジスタ。
FIG. 1 is a circuit diagram showing a computer system according to this invention, and FIG. 2 is a block connection diagram of a conventional computer system. 11 is a microprocessor, 13 is a decoder,
14 is a signal line, 15 is a switching element, and 20 is a transistor.
Claims (1)
記マイクロプロセツサから上記メモリ素子へ予め
定められたハイレベルまたはローレベルの活性信
号を伝送する信号線を具備したマイクロコンピユ
ータシステムにおいて、上記信号線の途中に、こ
の信号線を断続するスイツチング素子を設け、こ
のスイツチング素子が所定の動作モードに従つて
上記信号線をしや断したとき、上記メモリ側に接
続されている上記信号線を、ローレベルまたはハ
イレベルの非活性信号レベルの電圧源に接続する
ようにしたことを特徴とするマイクロコンピユー
タシステム。 (2) スイツチング素子がトランジスタであるこ
とを特徴とする実用新案登録請求の範囲第１項記
載のマイクロコンピユータシステム。[Claims for Utility Model Registration] (1) A microcomputer system comprising a microprocessor, a memory element, and a signal line for transmitting a predetermined high-level or low-level activation signal from the microprocessor to the memory element. A switching element is provided in the middle of the signal line to connect and disconnect the signal line, and when the switching element disconnects the signal line according to a predetermined operation mode, the signal line connected to the memory side is connected to the memory side. A microcomputer system characterized in that a signal line is connected to a voltage source at a low level or high level inactive signal level. (2) The microcomputer system according to claim 1, wherein the switching element is a transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10056786U JPS639632U (en) | 1986-06-30 | 1986-06-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10056786U JPS639632U (en) | 1986-06-30 | 1986-06-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS639632U true JPS639632U (en) | 1988-01-22 |
Family
ID=30970512
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10056786U Pending JPS639632U (en) | 1986-06-30 | 1986-06-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS639632U (en) |
-
1986
- 1986-06-30 JP JP10056786U patent/JPS639632U/ja active Pending
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