JPS6130146U - control circuit - Google Patents
control circuitInfo
- Publication number
- JPS6130146U JPS6130146U JP11548184U JP11548184U JPS6130146U JP S6130146 U JPS6130146 U JP S6130146U JP 11548184 U JP11548184 U JP 11548184U JP 11548184 U JP11548184 U JP 11548184U JP S6130146 U JPS6130146 U JP S6130146U
- Authority
- JP
- Japan
- Prior art keywords
- output
- input
- chip
- control circuit
- port
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Multi Processors (AREA)
- Information Transfer Systems (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案のワンチップマイクロコンピュータの接
続関係を示す回路図、第２図は従来のワンチップマイク
ロコイピュータの接続回路図、第３図は本考案の一実施
例である。
−１，２・・・・・・ワンチップマイクロコンピュータ
、３・・・・・・外部入力インタフェース、４・・・・
・，・外部出力インタフェース、５，６，９．１０・・
・・・・入出力ポート、１１．１２・・・・・・抵抗。FIG. 1 is a circuit diagram showing the connection relationship of a one-chip microcomputer of the present invention, FIG. 2 is a connection circuit diagram of a conventional one-chip microcomputer, and FIG. 3 is an embodiment of the present invention. -1, 2...One-chip microcomputer, 3...External input interface, 4...
・、・External output interface, 5, 6, 9.10...
...Input/output port, 11.12...Resistance.
Claims (1)
るシステムにおいて、当該ワンチップマイクロコンピュ
ニタ間に通信及び外部との入出力のためのシステムバス
を設けるに際して外部との人出力を行う当該一のワンチ
ップマイクロコンピュータの一つの入出力ポートを他の
ーのワンチップマイクロコンピュータの入力ポートに接
続すると同時に抵抗を介して外部入力インタフェースの
出力端子に接続し当該一のワンチップ÷イク口コンピュ
ータの他の入出力ポートは抵抗を介して当該他の一のワ
ンチップマイクロコンピュータの出カポートに接続する
とともに外部出力インタフェースの入力端子に接続する
ことを特徴とした制御回路。In a system controlled by multiple one-chip microcomputers, when a system bus is provided between the one-chip microcomputers for communication and input/output with the outside, the one-chip performs human output with the outside. One input/output port of a microcomputer is connected to the input port of another one-chip microcomputer, and at the same time it is connected to the output terminal of the external input interface via a resistor. A control circuit characterized in that an output port is connected to an output port of the other one-chip microcomputer via a resistor and also to an input terminal of an external output interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11548184U JPS6130146U (en) | 1984-07-27 | 1984-07-27 | control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11548184U JPS6130146U (en) | 1984-07-27 | 1984-07-27 | control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6130146U true JPS6130146U (en) | 1986-02-22 |
Family
ID=30674452
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11548184U Pending JPS6130146U (en) | 1984-07-27 | 1984-07-27 | control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6130146U (en) |
-
1984
- 1984-07-27 JP JP11548184U patent/JPS6130146U/en active Pending
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