JPS6116653U - Input/output circuit - Google Patents
Input/output circuitInfo
- Publication number
- JPS6116653U JPS6116653U JP10049984U JP10049984U JPS6116653U JP S6116653 U JPS6116653 U JP S6116653U JP 10049984 U JP10049984 U JP 10049984U JP 10049984 U JP10049984 U JP 10049984U JP S6116653 U JPS6116653 U JP S6116653U
- Authority
- JP
- Japan
- Prior art keywords
- input
- output circuit
- output
- terminal
- impedance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１区は本考案の入出力回路の回路図、第２図は従来の
入出力部回路構成の説明図である。
１・・・バスライン、２・・・双方向性トランシーバ、
７３・・・入出力端子、４・・・インピーダンス群、５
・・・ドライバ回路。The first section is a circuit diagram of the input/output circuit of the present invention, and FIG. 2 is an explanatory diagram of the conventional input/output section circuit configuration. 1... Bus line, 2... Bidirectional transceiver,
73...Input/output terminal, 4...Impedance group, 5
...Driver circuit.
Claims (1)
端子を入力又は出力の状態に制御可能に構成し、上記各
入出力端子にそれぞれ所定のインピーダシスを接続し、
該インピーダンスを介して電圧を印加し、上記入出力端
子の各々の端子につき、それそれ端子に接続された外部
素子のインピーダンスが当該端子の許容範囲内にあるか
否かの判定情報を出力し得るようにしたことを特徴とす
る入出力回路。In an input/output circuit having only a plurality of output terminals, each terminal is configured to be controllable to an input or output state, and a predetermined impedance is connected to each of the input/output terminals,
A voltage is applied through the impedance, and for each of the input/output terminals, it is possible to output determination information as to whether the impedance of the external element connected to the terminal is within the allowable range of the terminal. An input/output circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10049984U JPS6116653U (en) | 1984-07-03 | 1984-07-03 | Input/output circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10049984U JPS6116653U (en) | 1984-07-03 | 1984-07-03 | Input/output circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6116653U true JPS6116653U (en) | 1986-01-30 |
Family
ID=30659958
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10049984U Pending JPS6116653U (en) | 1984-07-03 | 1984-07-03 | Input/output circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6116653U (en) |
-
1984
- 1984-07-03 JP JP10049984U patent/JPS6116653U/en active Pending
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