JPS5885220U - data reading circuit - Google Patents
data reading circuitInfo
- Publication number
- JPS5885220U JPS5885220U JP17837881U JP17837881U JPS5885220U JP S5885220 U JPS5885220 U JP S5885220U JP 17837881 U JP17837881 U JP 17837881U JP 17837881 U JP17837881 U JP 17837881U JP S5885220 U JPS5885220 U JP S5885220U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- data reading
- reading circuit
- data
- input terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Power Sources (AREA)
- Devices For Supply Of Signal Current (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来から用いられているデータ読み取り回路の
一例を示す回路図、第２図〜第６図は本考案の一実施例
を示す回路図である。
１・・・・・・低消費電力形集積回路、２１〜２ｎ・・
・・・・抵抗素子、３・・・・・・データ設定部、４・
・・・・・インバータ、５．７・・・・・・抵抗、９・
・・・・・入力端子、１１・・・・・・データ読み取り
回路、１２・・・・・・ダイオード。FIG. 1 is a circuit diagram showing an example of a conventionally used data reading circuit, and FIGS. 2 to 6 are circuit diagrams showing an embodiment of the present invention. 1...Low power consumption integrated circuit, 21~2n...
...Resistance element, 3...Data setting section, 4.
...Inverter, 5.7...Resistor, 9.
...Input terminal, 11...Data reading circuit, 12...Diode.
Claims (1)
ともに、前記データ入力端子を抵抗素子によりプルアッ
プおよびプルダウンのいずれか一方の状態に設定するデ
ータ読み取り回路において、データ読み取り時だけ前記
抵抗素子と前記スイッチ回路を通る電流の通路を形成す
る回路を設けたことを特徴とするデータ読み取り回路。In a data reading circuit in which a switch circuit is connected to a data input terminal of an integrated circuit, and the data input terminal is set to either a pull-up or pull-down state by a resistor element, the resistor element and the switch are connected only when reading data. A data reading circuit comprising a circuit that forms a current path through the circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17837881U JPS5885220U (en) | 1981-11-30 | 1981-11-30 | data reading circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17837881U JPS5885220U (en) | 1981-11-30 | 1981-11-30 | data reading circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5885220U true JPS5885220U (en) | 1983-06-09 |
Family
ID=29973118
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17837881U Pending JPS5885220U (en) | 1981-11-30 | 1981-11-30 | data reading circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5885220U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53932A (en) * | 1976-06-25 | 1978-01-07 | Toshiba Corp | Encoder circuit |
| JPS559220A (en) * | 1978-06-30 | 1980-01-23 | Fujitsu Ltd | Keyboard system |
-
1981
- 1981-11-30 JP JP17837881U patent/JPS5885220U/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53932A (en) * | 1976-06-25 | 1978-01-07 | Toshiba Corp | Encoder circuit |
| JPS559220A (en) * | 1978-06-30 | 1980-01-23 | Fujitsu Ltd | Keyboard system |
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