JPS62112732U - - Google Patents
Info
- Publication number
- JPS62112732U JPS62112732U JP20446885U JP20446885U JPS62112732U JP S62112732 U JPS62112732 U JP S62112732U JP 20446885 U JP20446885 U JP 20446885U JP 20446885 U JP20446885 U JP 20446885U JP S62112732 U JPS62112732 U JP S62112732U
- Authority
- JP
- Japan
- Prior art keywords
- reset
- input
- terminal
- circuit
- circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001960 triggered effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 1
Description
第１図および第２図はこの考案のリセツト回路
の１実施例を示し、第１図は要部のブロツク図、
第２図は動作説明用の波形図、第３図および第４
図は従来のリセツト回路の結線図およびその動作
説明用波形図である。
１…入力端子、３…発振器、４…ＣＰＵ、５…
ワンシヨツトマルチバイブレータ、６，７…第１
、第２周辺回路、ＲＥＳＥＴ…リセツト端子。
1 and 2 show one embodiment of the reset circuit of this invention, and FIG. 1 is a block diagram of the main part,
Figure 2 is a waveform diagram for explaining operation, Figures 3 and 4.
The figure is a wiring diagram of a conventional reset circuit and a waveform diagram for explaining its operation. 1... Input terminal, 3... Oscillator, 4... CPU, 5...
One-shot multivibrator, 6th, 7th...1st
, second peripheral circuit, RESET...reset terminal.
Claims (1)
回路に供給される制御電圧が規定電圧以下のとき
出力されるパワーダウン信号が入力される入力端
子と、ＣＰＵの駆動用クロツク信号を出力する発
振器と、前記入力端子からのパワーダウン信号の
入力時に前記クロツク信号によりトリガされ前記
各回路をリセツトするパルス幅を有するリセツト
パルスを出力する再トリガ可能なワンシヨツトマ
ルチバイブレータと、前記各回路に設けられ前記
マルチバイブレータの出力端子にそれぞれ接続さ
れたリセツト端子とを備えたリセツト回路。 an input terminal to which a power-down signal that is output when the control voltage supplied to each circuit of a system using a microcomputer is below a specified voltage is input; an oscillator that outputs a clock signal for driving the CPU; and the input terminal. a retriggerable one-shot multivibrator that is triggered by the clock signal and outputs a reset pulse having a pulse width to reset each of the circuits when a power down signal is input from the circuit; and an output of the multivibrator provided in each of the circuits. and a reset terminal connected to each terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20446885U JPS62112732U (en) | 1985-12-27 | 1985-12-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20446885U JPS62112732U (en) | 1985-12-27 | 1985-12-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62112732U true JPS62112732U (en) | 1987-07-17 |
Family
ID=31170473
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20446885U Pending JPS62112732U (en) | 1985-12-27 | 1985-12-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62112732U (en) |
-
1985
- 1985-12-27 JP JP20446885U patent/JPS62112732U/ja active Pending
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