JPS6275521U - - Google Patents
Info
- Publication number
- JPS6275521U JPS6275521U JP1985167102U JP16710285U JPS6275521U JP S6275521 U JPS6275521 U JP S6275521U JP 1985167102 U JP1985167102 U JP 1985167102U JP 16710285 U JP16710285 U JP 16710285U JP S6275521 U JPS6275521 U JP S6275521U
- Authority
- JP
- Japan
- Prior art keywords
- microcomputer
- reset
- reset pulse
- power switch
- main power
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Selective Calling Equipment (AREA)
- Details Of Television Systems (AREA)
Description
図面はいずれも本考案の一実施例に関し、第1
図はリセツト回路の回路図、第2図はタイムチヤ
ート、第3図はリセツトパルス作成回路の機能ブ
ロツク図である。
2……主回路部、5……マイクロコンピユータ
、13……主電源スイツチ、20……SW入力検
出手段、21……立上り検出手段、22……60
msecカウンタ、23……出力ポートラツチ手
段。
The drawings all relate to one embodiment of the present invention.
FIG. 2 is a circuit diagram of the reset circuit, FIG. 2 is a time chart, and FIG. 3 is a functional block diagram of the reset pulse generating circuit. 2...Main circuit section, 5...Microcomputer, 13...Main power switch, 20...SW input detection means, 21...Rise detection means, 22...60
msec counter, 23...Output port latch means.
Claims (1)
るようにした電子機器の主回路部のオンオフを行
なう主電源スイツチの操作に応答してリセツトパ
ルスを発生し、このリセツトパルスを前記マイク
ロコンピユータのリセツト端子に供給してなるリ
セツト回路において、前記マイクロコンピユータ
が前記主電源スイツチのオフ状態を検出すると共
に、この検出出力に基づいてリセツトパルスを作
成することを特徴とするマイクロコンピユータの
リセツト回路。 A reset pulse is generated in response to the operation of a main power switch that turns on and off a main circuit section of an electronic device that constantly supplies operating power to a microcomputer, and this reset pulse is supplied to a reset terminal of the microcomputer. A reset circuit for a microcomputer, characterized in that the microcomputer detects the OFF state of the main power switch and generates a reset pulse based on this detection output.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1985167102U JPS6275521U (en) | 1985-10-30 | 1985-10-30 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1985167102U JPS6275521U (en) | 1985-10-30 | 1985-10-30 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6275521U true JPS6275521U (en) | 1987-05-14 |
Family
ID=31098718
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1985167102U Pending JPS6275521U (en) | 1985-10-30 | 1985-10-30 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6275521U (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50120518A (en) * | 1974-03-07 | 1975-09-20 | ||
JPS5329615A (en) * | 1976-09-01 | 1978-03-20 | Nippon Gakki Seizo Kk | Manual ciear unit |
JPS59174923A (en) * | 1983-03-25 | 1984-10-03 | Nec Corp | System for resetting information processing system |
-
1985
- 1985-10-30 JP JP1985167102U patent/JPS6275521U/ja active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50120518A (en) * | 1974-03-07 | 1975-09-20 | ||
JPS5329615A (en) * | 1976-09-01 | 1978-03-20 | Nippon Gakki Seizo Kk | Manual ciear unit |
JPS59174923A (en) * | 1983-03-25 | 1984-10-03 | Nec Corp | System for resetting information processing system |