JPH01146188U

JPH01146188U -

Info

Publication number: JPH01146188U
Application number: JP4359988U
Authority: JP
Priority date: 1988-03-30
Filing date: 1988-03-30
Publication date: 1989-10-09

Description

[Brief explanation of the drawing]

第１図はこの考案の一実施例による親子時計の
制御回路図、第２図は第１図の実施例の信号波形
図、第３図は従来の親子時計の制御回路図、第４
図は第３図の信号波形図を示す。図において、１は親時計のマスタークロツク、
２はドライバ、３〜６はパワートランジスタ、７
はスイツチングレギユレータ、８は子時計のスラ
ブクロツク、９は３０秒パルス信号、１０は６０
秒パルス信号、１１はリモートコントロール信号
、１２は子時計の制御信号である。なお、図中、
同一符号は同一、又は相当部分を示す。 Fig. 1 is a control circuit diagram of a parent-child clock according to an embodiment of this invention, Fig. 2 is a signal waveform diagram of the embodiment of Fig. 1, Fig. 3 is a control circuit diagram of a conventional parent-child clock, and Fig. 4 is a control circuit diagram of a parent-child clock according to an embodiment of the invention.
The figure shows the signal waveform diagram of FIG. In the figure, 1 is the master clock of the parent clock;
2 is a driver, 3 to 6 are power transistors, 7
is the switching regulator, 8 is the slave clock slab clock, 9 is the 30 second pulse signal, 10 is the 60
A second pulse signal, 11 a remote control signal, and 12 a slave clock control signal. In addition, in the figure,
The same reference numerals indicate the same or corresponding parts.

Claims

[Scope of utility model registration request]

In a timepiece device having a child clock controlled by an alternating current of a timepiece control circuit including one switching regulator and a switching circuit that alternates its output current, the control power source is one,
A control circuit for a parent-child clock characterized in that its outputs are alternately cross-crossed.