JPH02143843U - - Google Patents

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Publication number
JPH02143843U
JPH02143843U JP5121889U JP5121889U JPH02143843U JP H02143843 U JPH02143843 U JP H02143843U JP 5121889 U JP5121889 U JP 5121889U JP 5121889 U JP5121889 U JP 5121889U JP H02143843 U JPH02143843 U JP H02143843U
Authority
JP
Japan
Prior art keywords
input
input buffer
circuit
internal circuit
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5121889U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5121889U priority Critical patent/JPH02143843U/ja
Publication of JPH02143843U publication Critical patent/JPH02143843U/ja
Pending legal-status Critical Current

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  • Logic Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の実施例を示すブロツク図、第
2図は第1図に示すレベル保持回路の具体例を示
す図、第3図は第1図に示す入力バツフア周辺の
構成を示す図、第4図は電源オフ時の状態変化を
示すタイミングチヤートである。 1……入力バツフア、2……レベル保持回路。
FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a specific example of the level holding circuit shown in FIG. 1, and FIG. 3 is a diagram showing the configuration around the input buffer shown in FIG. 1. , FIG. 4 is a timing chart showing state changes when the power is turned off. 1...Input buffer, 2...Level holding circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 外部より到来する入力信号をバツフアリングし
、ゲート信号によつて入力信号と内部回路とを電
気的に絶縁する入力バツフアと、電源の状態を監
視し瞬時に高負荷がかかつたことを検出して上記
入力バツフアをゲートし、内部回路の入力レベル
を安定化するレベル保持回路とを具備することを
特徴とするゲートアレイのラツシユ電流制御回路
There is an input buffer that buffers input signals coming from the outside and electrically isolates the input signal from the internal circuit using a gate signal, and an input buffer that monitors the status of the power supply and instantly detects when a high load is applied. A gate array rush current control circuit comprising a level holding circuit that gates the input buffer and stabilizes the input level of the internal circuit.
JP5121889U 1989-04-28 1989-04-28 Pending JPH02143843U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5121889U JPH02143843U (en) 1989-04-28 1989-04-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5121889U JPH02143843U (en) 1989-04-28 1989-04-28

Publications (1)

Publication Number Publication Date
JPH02143843U true JPH02143843U (en) 1990-12-06

Family

ID=31570454

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5121889U Pending JPH02143843U (en) 1989-04-28 1989-04-28

Country Status (1)

Country Link
JP (1) JPH02143843U (en)

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