JPS6034653U - Central processing unit input/output port circuit - Google Patents

Central processing unit input/output port circuit

Info

Publication number
JPS6034653U
JPS6034653U JP12618083U JP12618083U JPS6034653U JP S6034653 U JPS6034653 U JP S6034653U JP 12618083 U JP12618083 U JP 12618083U JP 12618083 U JP12618083 U JP 12618083U JP S6034653 U JPS6034653 U JP S6034653U
Authority
JP
Japan
Prior art keywords
processing unit
central processing
output port
port circuit
unit input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12618083U
Other languages
Japanese (ja)
Other versions
JPH0124661Y2 (en
Inventor
和男 前田
Original Assignee
ユニデン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ユニデン株式会社 filed Critical ユニデン株式会社
Priority to JP12618083U priority Critical patent/JPS6034653U/en
Publication of JPS6034653U publication Critical patent/JPS6034653U/en
Application granted granted Critical
Publication of JPH0124661Y2 publication Critical patent/JPH0124661Y2/ja
Granted legal-status Critical Current

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  • Microcomputers (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

図面は本考案の一実施例の概略構成図である。 図中、１は中央処理ユニット、２はアナログ・スイッチ
乃至トランジスタ、３は演算増幅器、■１０は入出力ポ
ート、Ｒ１−Ｒ８は抵抗、である。The drawing is a schematic diagram of an embodiment of the present invention. In the figure, 1 is a central processing unit, 2 is an analog switch or transistor, 3 is an operational amplifier, 10 is an input/output port, and R1 to R8 are resistors.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 中央処理ユニットの入出力ポートの各々に対して備えら
れる入力モード時のプル・アップ抵抗に重みを付け、該
プル・アップ抵抗を出力モード時にデジタル−アナログ
変換用の重み付は抵抗として機能させるようにしたこと
を特徴とする中央処理ユニットの入出力ポート回路。A pull-up resistor provided for each input/output port of the central processing unit in an input mode is weighted, and the pull-up resistor is weighted to function as a resistor for digital-to-analog conversion in an output mode. An input/output port circuit for a central processing unit characterized by:
JP12618083U 1983-08-16 1983-08-16 Central processing unit input/output port circuit Granted JPS6034653U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12618083U JPS6034653U (en) 1983-08-16 1983-08-16 Central processing unit input/output port circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12618083U JPS6034653U (en) 1983-08-16 1983-08-16 Central processing unit input/output port circuit

Publications (2)

Publication Number Publication Date
JPS6034653U true JPS6034653U (en) 1985-03-09
JPH0124661Y2 JPH0124661Y2 (en) 1989-07-26

Family

ID=30287009

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12618083U Granted JPS6034653U (en) 1983-08-16 1983-08-16 Central processing unit input/output port circuit

Country Status (1)

Country Link
JP (1) JPS6034653U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0627736U (en) * 1992-09-14 1994-04-12 株式会社北海道ゴム工業所 Bar conveyor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0627736U (en) * 1992-09-14 1994-04-12 株式会社北海道ゴム工業所 Bar conveyor

Also Published As

Publication number Publication date
JPH0124661Y2 (en) 1989-07-26

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