JPS6284230U - - Google Patents
Info
- Publication number
- JPS6284230U JPS6284230U JP17384785U JP17384785U JPS6284230U JP S6284230 U JPS6284230 U JP S6284230U JP 17384785 U JP17384785 U JP 17384785U JP 17384785 U JP17384785 U JP 17384785U JP S6284230 U JPS6284230 U JP S6284230U
- Authority
- JP
- Japan
- Prior art keywords
- digital
- output
- ttl
- cmos
- waveform shaping
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000007493 shaping process Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Landscapes
- Logic Circuits (AREA)
Description
第1図は本考案の波形整形改善回路を示すブロ
ツク図、第2図はバーンイン装置に適用した本考
案及び従来の波形整形改善回路の波形図、第3図
は本考案の変形例を示すブロツク図、第4図は従
来の波形整形改善回路を示すブロツク図である。
1……デジタルTTLインバータ、2……デジ
タルTTLインバータ、3……デジタルCMOS
インバータ、4……デジタルCMOSバツフア、
5……デジタルTTLバツフア。
FIG. 1 is a block diagram showing the waveform shaping improvement circuit of the present invention, FIG. 2 is a waveform diagram of the present invention and the conventional waveform shaping improvement circuit applied to a burn-in device, and FIG. 3 is a block diagram showing a modification of the present invention. 4 are block diagrams showing a conventional waveform shaping improvement circuit. 1...Digital TTL inverter, 2...Digital TTL inverter, 3...Digital CMOS
Inverter, 4...Digital CMOS buffer,
5...Digital TTL buffer.
Claims (1)
ICと、回路の所定の個所に配置接続したデジタ
ルTTL―ICとを有し、前記デジタルCMOS
―ICの出力と前記デジタルTTL―ICの出力
とを接続してなることを特徴とする波形整形改善
回路。 Digital CMOS with output held at H level
IC, and a digital TTL-IC arranged and connected to a predetermined location of the circuit, and the digital CMOS
- A waveform shaping improvement circuit characterized in that the output of an IC is connected to the output of the digital TTL-IC.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17384785U JPS6284230U (en) | 1985-11-12 | 1985-11-12 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17384785U JPS6284230U (en) | 1985-11-12 | 1985-11-12 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6284230U true JPS6284230U (en) | 1987-05-29 |
Family
ID=31111690
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17384785U Pending JPS6284230U (en) | 1985-11-12 | 1985-11-12 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6284230U (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5733832A (en) * | 1980-08-06 | 1982-02-24 | Mitsubishi Electric Corp | Output circuit |
JPS5776923A (en) * | 1980-10-30 | 1982-05-14 | Oki Electric Ind Co Ltd | Signal input circuit |
-
1985
- 1985-11-12 JP JP17384785U patent/JPS6284230U/ja active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5733832A (en) * | 1980-08-06 | 1982-02-24 | Mitsubishi Electric Corp | Output circuit |
JPS5776923A (en) * | 1980-10-30 | 1982-05-14 | Oki Electric Ind Co Ltd | Signal input circuit |
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