JPH0193829U - - Google Patents
Info
- Publication number
- JPH0193829U JPH0193829U JP18934687U JP18934687U JPH0193829U JP H0193829 U JPH0193829 U JP H0193829U JP 18934687 U JP18934687 U JP 18934687U JP 18934687 U JP18934687 U JP 18934687U JP H0193829 U JPH0193829 U JP H0193829U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- power supply
- selects
- data signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000000295 complement effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 1
Description
第１図は従来のデジタル処理回路の回路図、第
２図は本考案の一実施例の回路構成説明図、第３
図は従来及び本考案の実施例による各入出力信号
を示すタイムチヤートである。
１，２，４，６，１２…ＦＥＴ、３，５，９，
１０…インバータ、８，１１，１３…アース、Ｉ
Ｎ…入力データ信号、ＣＯＮＴ…イネーブル信号
、ＯＵＴ…出力信号、ＶＤＯ…電源。
Figure 1 is a circuit diagram of a conventional digital processing circuit, Figure 2 is an explanatory diagram of a circuit configuration of an embodiment of the present invention, and Figure 3 is a circuit diagram of a conventional digital processing circuit.
The figure is a time chart showing each input/output signal according to the conventional method and the embodiment of the present invention. 1, 2, 4, 6, 12...FET, 3, 5, 9,
10... Inverter, 8, 11, 13... Earth, I
N...Input data signal, CONT...Enable signal, OUT...Output signal, VDO...Power supply.
Claims (1)
択する電源回路と、該電源回路出力を保持するラ
ツチ回路と、該ラツチ回路の後段に位置する相補
的なスイツチ回路とを備え、該スイツチ回路はデ
ータ信号により動作し、出力側の電位を直接上下
させることによつて前記保持による時間差を無く
したことを特徴とする高速データ処理回路。 A power supply circuit that selects an output according to an enable signal and a data signal, a latch circuit that holds the output of the power supply circuit, and a complementary switch circuit located after the latch circuit, and the switch circuit selects an output according to the data signal. 1. A high-speed data processing circuit, characterized in that the time difference caused by the holding is eliminated by directly raising and lowering the potential on the output side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18934687U JPH0193829U (en) | 1987-12-11 | 1987-12-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18934687U JPH0193829U (en) | 1987-12-11 | 1987-12-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0193829U true JPH0193829U (en) | 1989-06-20 |
Family
ID=31480384
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18934687U Pending JPH0193829U (en) | 1987-12-11 | 1987-12-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0193829U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09139657A (en) * | 1995-11-13 | 1997-05-27 | Oki Electric Ind Co Ltd | Latch circuit |
-
1987
- 1987-12-11 JP JP18934687U patent/JPH0193829U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09139657A (en) * | 1995-11-13 | 1997-05-27 | Oki Electric Ind Co Ltd | Latch circuit |
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