JPH0312527U - - Google Patents
Info
- Publication number
- JPH0312527U JPH0312527U JP7228589U JP7228589U JPH0312527U JP H0312527 U JPH0312527 U JP H0312527U JP 7228589 U JP7228589 U JP 7228589U JP 7228589 U JP7228589 U JP 7228589U JP H0312527 U JPH0312527 U JP H0312527U
- Authority
- JP
- Japan
- Prior art keywords
- inverter
- power supply
- output
- level
- delay
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Pulse Circuits (AREA)
Description
第１図は本考案の遅延制御回路を示す回路図、
第２図は第１図の各部波形を示すタイミングチヤ
ート、第３図は従来の遅延制御回路を示す回路図
、第４図は第３図の各部波形を示すタイミングチ
ヤートである。
５…バツフア、７…Ｎ−ＭＯＳ、８…インバー
タ、９…遅延回路。
FIG. 1 is a circuit diagram showing the delay control circuit of the present invention.
2 is a timing chart showing waveforms of various parts in FIG. 1, FIG. 3 is a circuit diagram showing a conventional delay control circuit, and FIG. 4 is a timing chart showing waveforms of various parts in FIG. 5...Buffer, 7...N-MOS, 8...Inverter, 9...Delay circuit.
Claims (1)
と、 入力が前記第１のインバータの出力と接続され
、入出力間の遅延量が遅延データに基づいて設定
される遅延回路と、 入力が前記遅延回路の出力と接続された第２の
インバータと、 第２の電源と前記第１のインバータの出力との
間に接続され、前記第２のインバータの出力に基
づいてオンオフ制御されるスイツチ回路と、 を備えたことを特徴とする遅延制御回路。 (2) 前記第１のインバータが持つ第１のスレツ
シヨルドレベルを前記第１の電源のレベルより小
に設定し、且つ前記第２のインバータが持つ第２
のスレツシヨルドレベルを前記第１の電源のレベ
ルより大に設定したことを特徴とする請求項(1)
記載の遅延制御回路。[Claims for Utility Model Registration] (1) A first inverter connected to a first power source, an input connected to an output of the first inverter, and a delay amount between input and output based on delay data. a second inverter whose input is connected to the output of the delay circuit; and an output of the second inverter connected between a second power supply and the output of the first inverter; A delay control circuit comprising: a switch circuit that performs on/off control based on; (2) The first threshold level of the first inverter is set to be lower than the level of the first power supply, and the second threshold level of the second inverter is set to be lower than the level of the first power supply.
Claim (1) characterized in that the threshold level of the first power supply is set higher than the level of the first power supply.
Delay control circuit as described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7228589U JPH0312527U (en) | 1989-06-20 | 1989-06-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7228589U JPH0312527U (en) | 1989-06-20 | 1989-06-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0312527U true JPH0312527U (en) | 1991-02-07 |
Family
ID=31610090
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7228589U Pending JPH0312527U (en) | 1989-06-20 | 1989-06-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0312527U (en) |
-
1989
- 1989-06-20 JP JP7228589U patent/JPH0312527U/ja active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS60180036U (en) | battery powered keyboard device | |
| JPH0312527U (en) | ||
| JPS58107633U (en) | Output circuit | |
| JPS61168446U (en) | ||
| JPS62192419U (en) | ||
| JPS60130541U (en) | Relay drive circuit | |
| JPS5828334U (en) | power circuit | |
| JPS59187027U (en) | switch circuit | |
| JPH0193829U (en) | ||
| JPS634127U (en) | ||
| JPS6112119U (en) | AC power controller | |
| JPS59152826U (en) | Clock oscillator control device | |
| JPH0273817U (en) | ||
| JPS643319U (en) | ||
| JPS58522U (en) | Pulse width shaping circuit | |
| JPS59119668U (en) | Frame pulse generation circuit | |
| JPS6384633U (en) | ||
| JPS5870650U (en) | relay control circuit | |
| JPH0386634U (en) | ||
| JPS6031673U (en) | Microcomputer frequency automatic discrimination circuit | |
| JPH01124719U (en) | ||
| JPS59118003U (en) | Control signal output circuit | |
| JPH0163224U (en) | ||
| JPS5866364U (en) | AC input detection circuit | |
| JPS59106228U (en) | A/D converter output guarantee circuit |