JPH0452244U - - Google Patents

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Publication number
JPH0452244U
JPH0452244U JP9279990U JP9279990U JPH0452244U JP H0452244 U JPH0452244 U JP H0452244U JP 9279990 U JP9279990 U JP 9279990U JP 9279990 U JP9279990 U JP 9279990U JP H0452244 U JPH0452244 U JP H0452244U
Authority
JP
Japan
Prior art keywords
introduces
adder
encoder
muntier
outputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9279990U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP9279990U priority Critical patent/JPH0452244U/ja
Publication of JPH0452244U publication Critical patent/JPH0452244U/ja
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示すブロツク線図
である。 1……パーソナルコンピユーター、2……シー
ケンサー、3……シフトレジスター、4……デー
タ設定部、5……加算器、6……マンチエスター
エンコーダー、7……パルストランス。
FIG. 1 is a block diagram showing one embodiment of the present invention. 1...Personal computer, 2...Sequencer, 3...Shift register, 4...Data setting section, 5...Adder, 6...Mantier encoder, 7...Pulse transformer.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] パーソナルコンピユーターにそれぞれ接続され
たシーケンサー、データ設定部にそれぞれ並列的
に接続された第1、第2、……の複数のシフトレ
ジスターと、上記各シフトレジスターの出力を順
次導入する加算器と、上記加算器の出力を導入す
るマンチエスターエンコーダーと、上記マンチエ
スターエンコーダーの出力を導入するパルストラ
ンスとを具え、入力されたパラレル信号をシリア
ル信号として出力することを特徴とするシステム
検証装置のシリアル信号発生器。
a sequencer connected to a personal computer, a plurality of first, second, etc. shift registers connected in parallel to a data setting section, an adder that sequentially introduces the outputs of each of the shift registers; Serial signal generation for a system verification device, characterized in that it comprises a Muntier star encoder that introduces the output of an adder, and a pulse transformer that introduces the output of the Muntier encoder, and outputs an input parallel signal as a serial signal. vessel.
JP9279990U 1990-09-04 1990-09-04 Pending JPH0452244U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9279990U JPH0452244U (en) 1990-09-04 1990-09-04

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9279990U JPH0452244U (en) 1990-09-04 1990-09-04

Publications (1)

Publication Number Publication Date
JPH0452244U true JPH0452244U (en) 1992-05-01

Family

ID=31829532

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9279990U Pending JPH0452244U (en) 1990-09-04 1990-09-04

Country Status (1)

Country Link
JP (1) JPH0452244U (en)

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