JPS6415186U

JPS6415186U -

Info

Publication number: JPS6415186U
Application number: JP10878987U
Authority: JP
Priority date: 1987-07-15
Filing date: 1987-07-15
Publication date: 1989-01-25

Description

[Brief explanation of the drawing]

第１図は、本考案の一実施例を示す図、第２図
は本考案の各部の信号を示す図、第３図は従来の
信号検出装置を示す図、第４図は従来の装置の各
部の信号を示す図である。図中の１，２，３はレジスタ、４，５，６は加
算器、７は平均値算出器、８は乗算器、９は比較
器、１０はメモリー、１１はメモリー制御器、Ｘ
_０〜Ｘ_６は各部の信号である。尚、図中同一ある
いは相当部分は同一符号で示してある。 FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing signals of various parts of the present invention, FIG. 3 is a diagram showing a conventional signal detection device, and FIG. 4 is a diagram of a conventional signal detection device. FIG. 3 is a diagram showing signals of each part. In the figure, 1, 2, 3 are registers, 4, 5, 6 are adders, 7 is an average value calculator, 8 is a multiplier, 9 is a comparator, 10 is a memory, 11 is a memory controller,
₀ to _X6 are signals of each part. In the drawings, the same or corresponding parts are indicated by the same reference numerals.

Claims

[Scope of utility model registration request]

a memory that stores an input signal, a first register of N stages that continuously delays the output of the memory, a second register that delays the output of the first register by one stage, and a second register that delays the output of the first register by one stage; a third register that successively delays output; a first adder that adds the N outputs of the first register; and a second adder that adds the N outputs of the third register. a third adder that adds the output of the first adder and the output of the second adder; an average value calculator that averages the output of the third adder; A multiplier that multiplies the output of the value calculator by a coefficient K, a memory controller that controls the memory, and a comparator that compares the output of the multiplier and the output of the second register. Signal detection device.