JPS62203484U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of this invention, and FIG. 2 shows a conventional device. In the figure, 1 and 2 are N-stage shift registers, 3 is a register, 4, 5, and 6 are adders, 7 is a multiplier, 8 is a comparator, and 9 is a multiplier generator. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Scope of utility model registration request] a first N-stage shift register that outputs N (N is an integer) time-series input signals before a certain time t;
A second N-stage shift register that outputs N time-series input signals after time t, a register that outputs a time-series input signal at time t, and N outputs of the first N-stage shift register. a first adder for adding together, a second adder for adding together the N outputs of the second N-stage shift register, and a third adder for adding each output of the first and second adders. an adder, a multiplier generator capable of changing the output value depending on time, a multiplier that multiplies each output of the third adder and the multiplier generator, and a multiplier that multiplies each output of the register and the multiplier. A signal detection device characterized by comprising a comparator for comparing sizes.