JPS58179546U

JPS58179546U - information processing equipment

Info

Publication number: JPS58179546U
Application number: JP7575982U
Authority: JP
Inventors: 野田　耕一郎
Original assignee: 株式会社京三製作所
Priority date: 1982-05-25
Filing date: 1982-05-25
Publication date: 1983-12-01
Also published as: JPS6220025Y2

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は本考案情報処理装置実施例の構成図、第２図は
プログラム実行順序を示すタイムチャートを示す図であ
る。１・・・非対称誤りデータ出力部、２・・・タイミング
信号出力部、３・・・１系演算処理部、４・・・２系演
算　　　“処理部、５・・・相補反転判断部、ＲＡ、　
ＲＢ・・−人力１ノ。レー、ｔ３・・・１系に与える交番形タイミング信号、
ｔ４・・・２系に与える交番形タイミング信号、Ａ・・
・正論理演算プログラム、”Ａ・・・負論理演算プログ
ラム、Ｐ３・・・１系の論理演算部の実行プログラム、
Ｐ４・・・２系の論理演算プログラムである。FIG. 1 is a block diagram of an embodiment of the information processing apparatus of the present invention, and FIG. 2 is a time chart showing the program execution order. DESCRIPTION OF SYMBOLS 1... Asymmetrical error data output unit, 2... Timing signal output unit, 3... 1st system arithmetic processing unit, 4... 2nd system arithmetic processing unit, 5... Complementary inversion determination unit, RA ,
RB... - Human power 1no. ray, t3...an alternating timing signal given to the 1 system,
t4... Alternating timing signal given to the 2nd system, A...
・Positive logic operation program, "A...Negative logic operation program, P3...1 system logic operation unit execution program,"
P4...2 type logical operation program.

Claims

[Scope of utility model registration request]

In an information processing device that performs arithmetic processing on input signals input through a plurality of relay contacts and outputs an output signal, an asymmetric error data output unit that outputs two series through predetermined relay contacts and a timing signal are output. It has a timing signal output section, a positive logic operation program, and a negative logic operation program, and based on the input from the asymmetric error data output section, performs the positive logic operation and the negative logic operation alternately in accordance with the output of the timing signal. The timing signal is output from the timing signal output section based on the input from the asymmetric error data output section. A positive logic operation and a negative logic operation are performed according to a timing signal inputted as a timing signal whose phase is inverted by 180 degrees from the timing signal inputted to the first system, and an alternating rectangular wave whose phase is inverted by 180 degrees from that of said first system is output. Based on the arithmetic processing unit of the 2nd system and the alternating human power from the 1st and 2nd systems, it is determined that there is a predetermined calculation output and output, and the inputs from the 1st and 2nd systems are not complementary inversion inputs. An information processing device comprising a complementary inversion determining section that sometimes determines that a predetermined calculation output is not present.