JPS6220025Y2 - - Google Patents

Description

[Detailed description of the invention] The present invention is an information processing device that performs arithmetic processing on input signals input through a plurality of relay contacts and outputs an output signal. It is related to.

Conventional electronic processing devices do not have a uniquely defined failure mode, and therefore, in a single processing system, when a failure occurs, the output cannot be shifted to a safe side. Therefore, as a method to obtain highly reliable output information, two processing devices perform calculation processing in parallel.
A method is known in which the outputs of two processing devices are checked to see if they match. However, even with this method, in the case of a fixed failure in both systems or a common intermittent failure in which both systems fail simultaneously due to noise, etc., there remains a possibility that the outputs of both systems will coincide with the error side, and safety cannot be guaranteed. This would violate the fail-safe principle of signal safety equipment.

The present invention aims to solve the above problems and provides an information processing device that realizes a fail-safe security function using an electronic computer processing device. An embodiment of the processing device will be described.

FIG. 1 is a configuration diagram of the information processing device of the present invention.
In Fig. 1, 1 indicates 2 through a predetermined relay contact.
It is an asymmetric error data output unit that outputs to the series,
One example is an input device based on an asymmetric error data input method disclosed in Japanese Patent Application No. 56-162104 by the same applicant. The above asymmetric error data input method is “H”,
The output of the oscillator OSC, which generates a square wave alternating current signal that repeats "L", is given to the semiconductor circuit via the operating contact of a predetermined relay, and when the predetermined relay is operating, the output of the oscillator OSC is is “H”,
If "L" is repeated, the output changes to "L" and "H" repeatedly, but if the relay including the relay contact and the semiconductor circuit fail, the repeated output disappears.This is an asymmetric error data input method. and RB indicate the contacts of the above-mentioned predetermined relay. 2 has a timing signal output unit that outputs a timing signal; 3 has a positive logic operation program and a negative logic operation program; and outputs a timing signal from the timing signal output unit 2 based on the input from the asymmetric error data output unit 1. 4 has a positive logic operation program and a negative logic operation program, and 4 has a positive logic operation program and a negative logic operation program. Based on the input, the timing signal output from the timing signal output section 2 is converted into a timing signal input as a timing signal with a 180° phase inversion of the timing signal input to the first system arithmetic processing section. Therefore, the second system arithmetic processing unit A executes positive logic operations and negative logic operations and outputs an alternating rectangular wave whose phase is 180° inverted from that of the first system.
indicates a positive logic operation program, and indicates a negative logic operation program. 5 determines that there is a predetermined calculation output when the input from the 1st and 2nd system arithmetic processing units is an alternating square wave with complementary inversion, and outputs it, and the input from the 1st and 2nd system arithmetic processing units is complementary inverted. This is a complementary inversion determining section that determines that there is no predetermined calculation output when the wave is not an alternating square wave.An example is a mismatch circuit in Japanese Patent Application No. 175063 filed by the same applicant, in which the phases of two repetitive input signals are complementary to each other. This is a mismatch circuit that outputs a command signal only when the FIG. 2 is a diagram showing a time chart showing the program execution order, and the operation of the information processing apparatus of the present invention will be explained with reference to FIGS. 1 and 2.

The inputs of the first asymmetric error data output section are predetermined relay contacts RA and RB. A timing signal output section 2 provided between the logic operation section of the 1st system and the logic operation section of the 2nd system outputs two alternating timing signals with a constant cycle in consideration of the repetition period of the positive logic operation program A and the negative logic operation program. are output so that they are complementary to each other, and the 1st and 2nd systems are
Provided to the logical operation section of the system. What to give to the 1st system
Let t ₃ be the one given to the 2nd system as t ₄ . 1 series and 2
Each logic operation section of the system receives a timing signal.
When t ₃ and t ₄ are set, positive logic operation program A
is executed, and when it is reset, the negative logic operation program is executed. In FIG. 2, P ₃ indicates an execution program of the logic operation section of the first system, and P ₄ indicates an execution program of the logic operation section of the second system. Next, the processing of the positive logic operation program A and the negative logic operation program will be explained.

If the two states of information are "true" and "false", the input relay contact of the asymmetric error data output section 1
The RA and RB inputs are connected so that when the input information is "true", the input relays RA and RB are activated and the contacts are ON. Regarding the output information of the complementary inversion determination unit 5, when the information is "true", there is an output, and when the information is "false", there is no output. In the positive logic operation program A of the arithmetic processing unit, when the input state of the input information is "true", logic "1" is assigned, and when the result of the operation is true, the logic is set to "1". erect In other words, if we take as an example an operation that makes the result true when the input states of two input information are true, in a positive logic operation, when both input information are logic "1", the operation result will be logic "1", and either When the input is logic "0", the operation result is a logical AND operation such that the result is logic "0". Conversely, in the negative logic operation program, when the input state of the input information is "true", logic "0" is assigned, and when the result of the operation is "true", the logic is assembled using negative logic. In other words, if we take an example of an operation that makes the result of an operation "true" when the input states of two input information are "true", in a negative logic operation, when both inputs are logic "0", the result of the operation is logic "0".
Therefore, when either input is logic "1", the operation result is a logical sum operation such that the logic "1" is obtained. After defining "true" and "false" of input and output information in this way, the processing of the program will be explained.

The positive logic operation program A in each of the arithmetic processing units of the 1st and 2nd systems consists of input processing, positive logic operation processing, and output processing. Since the signal level of the common line input to the section changes from "L" to "H", if the input state changes from "1" to "0" correspondingly, the input relay contact turns ON. In other words, since the input information is "true", it is stored as "1", and if the input state does not change like "1" and "1" or "0" and "0", the relay contact is turned OFF or the input section is turned off. Since it is a fixed failure, the input information is regarded as "false" and "0" is stored. Next, a positive logic operation is performed based on this input information, and if the result is a logic "1", that is, the information is "true", "1" is output, and "0" is output.
That is, if it is "false", the previous state, that is, the state output by the negative logic operation program is maintained. The negative logic operation program consists of input processing, positive logic operation processing, and output processing. In the input processing, input judgment is performed in the same procedure as the A program, and if the input information is "true", logic "0" is stored, If “false”, “1” is stored. Next, a negative logic operation is performed based on this input information, and if the result is logic "0", that is, the information is "true", "0" is output, and if it is "1", that is, "false", then the previous Maintain the output state of the program. When the A program and the program configured in this way are executed alternately, when the operation result is "true", logic "1" and logic "0" are output alternately from the respective processing units of the 1st and 2nd systems. Therefore, the output signal level is repeatedly inverted to "L" and "H", and when the operation result is "false", both the positive and negative programs of the processing units of the 1st and 2nd systems do not output new outputs. Therefore, the output signal level maintains the "L" or "H" state. The repeat execution order of the program A and program above is reversed between the 1st and 2nd system arithmetic processing units, so while the calculation result from the arithmetic processing unit should be “true”, the 1st and 2nd system Complementary inversion outputs similar to the timing signals t ₃ and t ₄ of the synchronization control unit are output from the arithmetic processing unit, and while they should be “false”, they are “H” - “H” or “H” from the 1st and 2nd systems. A fixed signal of either -“L”, “L”-“H”, or “L”-“L” is output. The outputs from the 1st system arithmetic processing section and the 2nd system arithmetic processing section are input to the complementary inversion judgment section 5.
A command signal is output only when the phases of two alternating rectangular waves, that is, two repetitive input signals, are complementary to each other.

Next, failure modes will be explained. By assigning "false", that is, relay contact OFF, to the safe side for the input of the asymmetric error data output unit 1, regardless of the actual input conditions,
Since the fixed failure state of the input section is treated as input information "false", the output can be shifted to the safe side. Furthermore, by assigning the no-output state to the output from the complementary inversion determining section 5, at least one inversion signal will stop in the event of a fixed failure in the output section, regardless of the actual processing result. The output information is determined to be “false” and the system transitions to the safe side. In addition, in the case of a common intermittent fault, even if it is assumed that the programs in the 1st and 2nd system arithmetic processing units happen to be executing the same processing steps, they are in a complementary relationship due to positive logic operations and negative logic operations. In order to perform calculations based on certain information, either the 1st or 2nd system arithmetic processing unit will make a mistake, so the complementary inversion output will collapse and the output information will be judged as “false”, resulting in a safe side. Transition.

The information processing device of the present invention is constructed using an electronic computer type processing device as described above, and is used in signal safety equipment such as interlocking devices for railway signals, etc., in order to provide no predetermined calculation output in both fixed failures and common intermittent failures. It is used to realize an electronic information processing device with fail-safe security functions.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an embodiment of the information processing device of the present invention.
FIG. 2 is a diagram showing a time chart showing the program execution order. 1...Asymmetrical error data output unit, 2...Timing signal output unit, 3...1 system calculation processing unit, 4...
2-system arithmetic processing section, 5...complementary inversion judgment section, RA,
RB...Input relay, _t3 ...Alternating timing signal given to the 1st system, _t4 ...Alternating timing signal given to the 2nd system, A...Positive logic operation program,...
... Negative logic operation program, P ₃ ... Execution program of the logic operation section of the 1st system, P ₄ ... Logical operation program of the 2nd system.

Claims (1)

[Scope of utility model registration request] In an information processing device that performs arithmetic processing on input signals input through a plurality of relay contacts and outputs an output signal, an asymmetric error data output unit that outputs two series through predetermined relay contacts and a timing signal are output. It has a timing signal output section, a positive logic operation program, and a negative logic operation program, and alternately executes positive logic operation and negative logic operation according to the output of the timing signal based on the input from the asymmetric error data output section. It has a first-system arithmetic processing section that outputs an alternating rectangular wave, a positive logic operation program, and a negative logic operation program, and a timing signal outputted from the timing signal output section based on the input from the asymmetric error data output section. A positive logic operation and a negative logic operation are performed according to a timing signal input as a timing signal whose phase is reversed by 180 degrees from the timing signal input to the first system, and an alternating rectangular wave whose phase is reversed by 180 degrees from that of the first system is generated. and a calculation processing unit of the second system which outputs a predetermined calculation output based on the alternating inputs from the first and second systems, and outputs it when the input from the first and second systems is not a complementary inversion input. An information processing device comprising a complementary inversion determination unit that determines that there is no predetermined calculation output.