JPS61262911A - Input noise detecting circuit - Google Patents

Abstract

PURPOSE:To prevent a malfunction due to an input noise by deciding a latched data as a noise if the different comparison data are obtained between said latched data and the n-th latched data signal after latching said single data. CONSTITUTION:If the 1st-3rd pulses of a data signal are equal to a single data, the output of the 1st latch circuit 1 is set at 1 by the single data on the 1st pulse. Then the single data on the 2nd pulse of the data signal is latched by the 2nd latch circuit 3 by the load signal of the 1st logical circuit 2. Thus the output of the circuit 3 is equal to 1. The outputs of both circuits 1 and 3 are compared with each other by a comparator 4. In this case, the coincidence is obtained between both outputs with 1. Thus the data signal is decided as normal and the 2nd logical circuit 5 delivers no system reset signal. If the 1st-3rd pulses of the data signal are equal to 0 and the output of the circuit 1 is equal to 1 owing to the 1st pulse, no coincidence is obtained between the outputs of circuits 1 and 3 through the comparator 4 since the 2nd pulse is equal to data 0. Thus a noise detecting circuit decides a noise and delivers the system reset signal.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an input noise detection circuit for a system that receives as input a data signal that is a constant periodic pulse train when the data is lJ++ and is high level - or low level when the data is 0''. It is related to.

2. Description of the Related Art Conventionally, this type of input noise detection circuit has been constructed by simply connecting an R-S flip-flop to the key matrix output in a circuit using a key matrix as shown in FIG. Fifth
In the case shown in the figure, even if the key matrix output signal is affected by chattering, once the R3/\-N-S flip-flop is senodled, its output becomes 1'', so there is no effect of chattering caused by the data signal. .Furthermore, the R-S flip-flop is reset by a reset signal from the system at appropriate times.As mentioned above, in the past, it was only used to prevent chattering.

Problems to be Solved by the Invention As described above, with the conventional configuration, it is possible to prevent chattering, but if there is noise on the input signal,
The system could misidentify noise as data, causing malfunctions. The present invention is intended to solve these problems, and aims to prevent malfunctions caused by input noise.

Means for Solving All Problems In order to solve this problem, the present invention provides that after a system reset, when the data is '1°2, m pulse trains of a constant period are used as input data signals, and the data is "0". ”, a first latch circuit that takes a high level or low level as an input data signal, a second latch circuit that latches a data signal at the n-th pulse timing (m≧n), and a second latch circuit that latches the data signal at the n-th pulse timing. a first logic circuit that generates a load signal for latching a signal to a second latch circuit; and a timing signal for checking a comparison result between the output of the first latch circuit and the output of the second latch circuit after the load signal; If the outputs of the first latch circuit and the second latch circuit are different from each other based on the results of the comparator, the outputs of the first latch circuit and the second latch circuit are different. 1°' data is determined to be noise, a system reset signal is generated at the timing of the check signal, and when the outputs of the first latch circuit and the second latch circuit match, the IJI+ data latched by the first latch circuit is processed as normal. a second logic circuit that determines that it is an input signal and holds 1"data; and when the second logic circuit outputs a system reset signal or when the system outputs a reset signal, a first latch circuit; It is composed of a second latch circuit, a first logic circuit, and a reset circuit that resets the system.

Operation With this configuration, the latched "1'" after system reset
' Compare the data with the data signal latched at the nth timing after the "1" data is latched, and if the comparison results are different, the 1" data latched by the first latch circuit is judged as noise and the system is reset. The system is reset by the signal.If the comparison results match, the 111++ data latched by the first latch circuit is determined to be normal, and the system is reset by the signal.

Embodiment FIG. 1 is a block diagram of an input noise detection circuit according to an embodiment of the present invention. The block includes a first latch circuit 1 to which m pulse train data signals of a constant period are input, and a first logic circuit which inputs the output of the first latch circuit 1 and a clock signal and generates a load signal and a check signal. A circuit 2, a second latch circuit 3 which functions according to the load signal, a comparator 6 for comparing the respective outputs of the first latch circuit 1 and the second latch circuit 3; , a functioning second logic circuit 5 and the first latch circuit 1
, the second latch circuit 3, and the first logic circuit 2, respectively i I
A reset circuit 6 is provided which is set on the J, and the reset circuit 6 functions by a signal from the system 7. Second
The figure is a specific logic circuit diagram of an input noise detection circuit according to an embodiment of the present invention. FIG. 3 shows a timing chart when a normal signal is input to this circuit configuration. In Figure 3, if the 1st, 2nd, and 3rd pulses of the data signal are 1''' data, the 1st pulse after the system reset is
The first latch circuit (R-87 lip flop 8) is set by the "1" data, and its output becomes "1".

First logic circuit (AND game) 14, 15. IJ-1 = T flip-flop with isolation 16-18, OR gate 1
9), the second latch circuit (inverter 10, NOR gate 11...
The R-S flip-flop 9) latches 7.\-7 and the output B becomes 11111. The first and second latch circuit outputs A, B-(i7 comparator (EXOR gate 1
2), and the comparison result is checked by a second logic circuit (AND gate 13) at the timing of the check signal generated by the first logic circuit. In this case, the first latch circuit output and the second latch circuit output B are lJ! +
Since they match, the data signal is determined to be normal and the second logic circuit (AND gate 13) does not output a system reset signal.

Next, if the 1st, 2nd, and 3rd pulses of the data signal are 'O''' data, and the switching data signal is fixed at a low level, after the system reset, if the first pulse is fl 111 due to noise generation. The first latch circuit 1 is set, and its output A becomes 1'', as shown in the timing chart of FIG. 4 when data is generated. Since the second pulse is "O" data, the second latch circuit 3 is not set and its output B is "0". Since the output results of the first and second latch circuits are different, the second logic circuit 6 determines that it is noise and outputs a system reset signal. In addition, the first and second latch circuits and the first logic circuit are reset through the system reset signal (OR gate) 20).

Note that fixing the data signal to a high level is the second
This must be avoided in the circuit of the illustrated embodiment. This is because the first and second latch circuits latch the high level and completely lose the noise detection function.

Although the embodiments shown in FIGS. 2 to 4 are explained using positive logic, if the logic configuration of FIG. 2 is changed to negative logic, each input cover turn can be changed to negative polarity.

Effects of the Invention As described above, according to the present invention, even if an abnormality occurs due to an input data signal change, malfunction of the system can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an input noise detection circuit according to an embodiment of the present invention and a system reset circuit, FIG. 2 is a logic configuration diagram showing an input noise detection circuit according to an embodiment, and FIG. 3 is a normal block diagram. FIG. 4 is a timing chart showing an abnormal input signal, and FIG. 6 is a circuit diagram showing a conventional technique. 1...First latch circuit, 2...First logic circuit, 3...Second latch circuit, 4......
Comparator, 5... Second logic circuit, 6... Reset circuit, 7... System, 8, 9... R-S flip-flop, 1o... Inverter, 11...
NOR gate, 12...xxou game), 13~
15--A N D gate, 16-18... T flip-flop with reset, 19.20...O
R game), 21... system.

Claims (1)

[Claims] A first pulse train whose input data signal is m pulse trains with a constant period.
A second latch circuit that latches a data signal at the timing of the n-th pulse (m≧n) of the same pulse train as a latch circuit, and a load signal that latches the data signal to the second latch circuit at the timing of the n-th pulse. and after the load signal, the outputs of the first latch circuit and the second latch circuit are compared with a first logic circuit that generates a timing signal for checking a comparison result between the output of the first latch circuit and the output of the second latch circuit. If the outputs of the first latch circuit and the second latch circuit differ from the results of the comparator and the comparator, the "1" data latched by the first latch circuit is determined to be noise, and the system is activated at the timing of the check signal. When a reset signal is generated and the outputs of the first latch circuit and the second latch circuit match, the first latch circuit is latched.
A second logic circuit that determines that the "1" data is a normal input signal and determines that the "1" data is held and the second logic circuit outputs a system reset signal, or the system outputs a reset signal. An input noise detection circuit comprising: the first latch circuit, the second latch circuit, the first logic circuit, and a reset circuit for resetting the system.