JPH0719187B2 - Logic circuit - Google Patents

Description

The present invention relates to a logic circuit that is reset by a system reset signal that resets the entire system and a reset signal caused by a predetermined reset factor.

(Prior Art) Conventionally, as a technology in such a field, there is one described in JP-A-58-221421.

FIG. 2 is a block diagram showing a configuration example of a conventional 1-chip microcomputer which is a kind of logic circuit.

The 1-chip microcomputer 1 is provided with a reset input terminal 2 for inputting a system reset signal that resets the entire system. This system reset signal is sent to the timing controller 6, the register 7, the port 8 and the LCD via the inverter 3 and the OR gate 5.
It is input to each logic block such as the (liquid crystal) driver 9. The runaway detection circuit 4 is a circuit that detects whether or not the program has run away. The runaway detection circuit 4 has an instruction code for decoding the instruction from the instruction register 11.
The signal from 10 is input. When the runaway detection circuit 4 detects a program runaway, a reset signal is generated,
This reset signal, like the system reset signal,
It is inputted to the logic block such as the timing controller 6, the register 7, the port 8 and the LCD driver 9 via the OR gate 5.

The operation of the microcomputer configured as described above will be described with reference to the timing chart of FIG.

When the system reset signal is input from the reset input terminal 2, the system reset signal is input to the logic block such as the timing controller 6, the register 7, the port 8 and the LCD driver 9 via the inverter 3 and the ORGAP 5, and each logic block is Will be reset.

After the system is reset, the normal operation is started, and when a predetermined program is executed, instructions are sequentially set in the instruction register 11 and the instruction decoder 10 decodes the instructions.

On the other hand, a timing signal is output from the instruction register 11 via the instruction decoder 10 at regular intervals. The runaway detection circuit 4 detects the timing signal, and when the timing signal is input in a constant cycle, determines that the program is operating normally. However, when the program starts the runaway (time point) and enters an infinite loop or the like, the timing signal is not output from the instruction register 11 to the runaway detection circuit 4. Therefore, the runaway detection circuit 4 determines that the runaway operation is in progress (time point), and outputs a reset signal. This reset signal is sent to the timing controller 6, register 7, port 8 and LCD driver 9 via the OR gate 5.
Are input to the logical blocks, and these logical blocks are reset.

(Problems to be Solved by the Invention) However, in a conventional microcomputer, a program is caused by a malfunction of a logic block such as a timing controller 6, a register 7, an instruction decoder 10 and an instruction register 11 which controls reading, decoding and execution of the program. If a runaway occurs, it is detected by the runaway detection circuit 4 and a reset signal is output. As with the system reset signal, everything including the port 8 controlling the input / output device (not shown) and the LCD driver 9 etc. However, there is a problem that the logical blocks of are reset and the ports 8 and the LCD driver 9 and the like cannot be synchronized with the input / output device.

That is, when the display driver such as the LCD driver 9 or the FLT (fluorescent display tube) driver in the logic block is reset, the display duty ratio is changed or the scan output of the display is stopped. Disappears or lights up incorrectly. Especially in the case of the LCD driver 9, a DC component is applied to the LCD. In the case of input / output port 8,
When the logic block for setting the input / output mode of the terminal is reset, the terminal used as the input mode is reset to the output mode, data may collide, and an excessive current may flow.

Furthermore, when operating while transferring data to another microcomputer or the like, if all the logic blocks are reset by the reset signal from the runaway detection circuit 4, synchronization with that microcomputer will be achieved. It will be lost and the data transfer will be incorrect.

SUMMARY OF THE INVENTION The present invention provides a logic circuit that solves a problem that the above-mentioned conventional technique has, in that it avoids the influence on input / output devices and the like caused by resetting the entire logic circuit for stopping and recovering program runaway. It is provided.

(Means for Solving Problems) In order to solve the above problems, the present invention controls, in a logic circuit, a first logic block that controls an input / output device and a program read, decode, and execution. Also, the runaway of the second logic block that controls the first logic block and the program caused by the malfunction of the second logic block is detected, and the second logic block is reset based on the detection result. A runaway detection circuit for giving a program runaway reset signal to the second logic block for resetting, and a system reset terminal provided with a system reset signal for resetting the first and second logic blocks when power is turned on. I have it.

(Operation) According to the present invention, since the logic circuit is configured as described above, when the system reset signal is input to the system reset terminal when the power is turned on, the first and second logic blocks are reset and the normal operation is performed. Move to. During normal operation, for example, when the program runs out of control due to a malfunction of the second logic block, it is detected by the runaway detecting circuit and the program runaway reset signal is output from the runaway detecting circuit. When the program runaway reset signal is output, the second
The logic block of is reset, and the execution of the program being executed stops. At this time, since the first logical block is not reset, the input / output device controlled by the first logical block can be synchronized with the first logical block. Therefore, the above problems can be eliminated.

(Embodiment) FIG. 1 is a configuration block diagram of a logic circuit showing an embodiment of the present invention. This logic circuit is a one-chip microcomputer as in the conventional FIG. 2, and elements common to those in FIG. 2 are designated by common reference numerals.

The 1-chip microcomputer 1 is provided with a system reset terminal (that is, a reset input terminal) 2 for inputting a system reset signal for resetting the entire system. This system reset signal is amplified by the inverter 3, input to the OR gate 5, and also input to the port 8 and the first logic block such as the LCD driver 9. The first logic block has a function of controlling an input / output device such as an LCD (not shown).

The runaway detection circuit 4 is a circuit that detects runaway of a block caused by a malfunction of the second logic block such as the timing controller 6, the register 7, the instruction decoder 10 and the instruction register 11, and generates a program runaway reset signal. The second logical block is the program read,
It has a function of controlling decoding and execution, and of controlling the first logic block. A signal from the instruction decoder 10 for decoding the instruction from the instruction register 11 is input to the runaway detection circuit 4. When the runaway detection circuit 4 detects a runaway, a program runaway reset signal is generated and input to the OR gate 5. The program runaway reset signal is output to the reset output terminal 14 via the inverter 13. The OR gate 5, which inputs the system reset signal and the program runaway reset signal,
It is connected to the timing controller 6 and the register 7.

Here, the first logic block is a logic block that should be reset only by a system reset signal, and the second logic block is a logic block that should also be reset by a program runaway reset signal from the runaway detection circuit 4. It is a block.

A flip-flop 12 is connected to the output side of the runaway detection circuit 4. The flip-flop 12 is for indicating by which reset signal the microcomputer 1 has been reset. The power supply VDD is input to the data input terminal D of the flip-flop 12 and the runaway detection circuit 4 receives the clock input terminal φ. A reset signal is input and a system reset signal is input to the reset input terminal R.

Next, the operation of this embodiment will be described with reference to the timing chart of FIG.

When the power is turned on, a system reset signal is externally input to the reset input terminal 2. This system reset signal is input to the timing controller 6 and the register 7 which are the second logic block via the OR gate 5, and also the port 8 and the LC which are the first logic block.
It is directly input to the D driver 9 or the like. Then, all of these logic blocks 6, 7, 8, 9 etc. are reset. Further, the system reset signal is the flip-flop 12
Is reset, and the L level is output from the flip-flop 12.

Next, when the normal operation is started and a predetermined program is executed, instructions are sequentially set in the instruction register 11, and the instruction decoder 10 decodes the instructions. The predetermined program stores an instruction for generating a timing signal to the runaway detection circuit 4 at regular intervals. Therefore, in normal operation, the instruction decoder 10 outputs a timing signal at regular intervals. The runaway detection circuit 4 detects this timing signal, determines that it is operating normally when input at a constant cycle, and does not output the program runaway reset signal.

However, if the program starts a runaway for some reason (for example, a malfunction of the timing controller 6, the register 7, etc.) and enters an infinite loop, the instruction register 11 does not store the instruction for generating the timing signal. The timing signal is not generated from the instruction decoder 10. When a certain time elapses after the timing signal is not input (time point), the runaway detection circuit 4 determines that the program has run out and outputs a program runaway reset signal. The program runaway reset signal is input to the timing controller 6 and the register 7 which are the second logic block via the OR gate 5, and the logic blocks 6 and 7 are reset. However, since the program runaway reset signal is not input to the port 8 and the LCD driver 9 which are the first logic blocks, these logic blocks 8 and 9 are not reset and the above-mentioned problem does not occur.

Further, the program runaway reset signal is output from the reset output terminal 14 in the form of a reset output signal via the inverter 13, and it can be known from the outside that the microcomputer 1 has runaway. Further, the program runaway reset signal is input to the clock input terminal φ of the flip-flop 12, and the output signal of the flip-flop 12 becomes H level. By reading the contents of this flip-flop 12, it is possible to detect that the program has runaway.

As described above, in this embodiment, the following advantages (a) to
There is (c).

(A) When the program runs out of control, the timing controller 6, the register 7, etc. are reset, and the runaway of the program can be stopped. At this time, the port 8 controlling the input / output device such as LCD, the LCD driver 9 and the like are not reset, so that data collision, display off, erroneous turn off, and application of the DC component to the LCD at the port 8 are not reset. It is possible to avoid the problem of being out of synchronization such as.

(B) From the signal from the reset output terminal 14, it can be known from the outside that a reset factor (program runaway in this case) has occurred internally. Therefore, when it is operated in combination with another microcomputer, the other microcomputer can operate while confirming the runaway of the program, resulting in a fatal accident such as loss of synchronization or transfer of the data. It can be avoided.

(C) By reading the contents of the flip-flop 12, it is possible to know what the reset factor is, and it is possible to set the initial value corresponding thereto.

The present invention is not limited to the above embodiment, and various modifications can be made. The following are examples of such modifications.

(I) The reset signal generation circuit may be a circuit that generates a reset signal according to another reset factor such as a power supply voltage drop, in addition to the runaway detection circuit 4. in this case,
The logic block to be reset is determined according to the reset factor.

Further, by providing the flip-flop 12 for each reset factor, it is possible to know which reset factor caused the reset.

(Ii) The logic circuit of the present invention is not limited to the one-chip microcomputer 1, but may be a multi-chip microcomputer,
It can also be applied to a general logic circuit that is reset.

(Effects of the Invention) As described in detail above, according to the present invention, for example,
When the program goes out of control due to a malfunction of the second logic block that controls the reading, decoding, execution, etc. of the program, the runaway detection circuit gives a program runaway reset signal to the second logic block to reset the program. The program runaway reset signal is not applied to the first logic block for controlling the device.
Therefore, when the second logic block is reset by the program runaway reset signal, the program runaway is stopped. In this way, when the execution of the program being executed is stopped, the program runaway reset signal becomes the first
, The first logic block does not reset.

As a result, the problem that the first logic block and the input / output device controlled by the first logic block cannot be synchronized (for example, when the LCD driver is reset, the display duty ratio changes or the display scan output is changed). The display disappears or lights up incorrectly because the LCD stops.
It is possible to accurately avoid the problem that a DC component is applied to the first logic block and to synchronize the input / output device with the first logic block.

Further, by providing a terminal for outputting the output signal of the runaway detection circuit to the outside, it can be known from the outside that the runaway of the program has occurred inside the logic circuit. Therefore, when operating in combination with other logic circuits, other logic circuits can operate while confirming program runaway, which may cause fatal accidents such as loss of synchronization and transfer of erroneous data. Can be avoided exactly.

[Brief description of drawings]

FIG. 1 is a block diagram of a microcomputer showing an embodiment of the present invention, FIG. 2 is a block diagram of a conventional microcomputer, FIG. 3 is a timing chart showing the operation of FIG. 2, and FIG. 3 is a timing chart showing the operation of FIG. 1. 1 ... Microcomputer, 2 ... Reset input terminal, 3 ... Inverter, 4 ... Runaway detection circuit, 5 ... OR gate, 6 ... Timing controller, 7 ... Register, 8 ... Port, 9 ... LCD Driver, 10 ... instruction decoder, 11 ... instruction register, 12 ... flip-flop, 13 ... inverter, 14 ... reset output terminal.

Claims (1)

[Claims] 1. A first logic block for controlling an input / output device, a second logic block for controlling reading, decoding, and execution of a program and controlling the first logic block, and a second logic block. A runaway detection circuit that detects a runaway of the program caused by a malfunction of a block and provides a program runaway reset signal for resetting the second logic block based on the detection result to the second logic block, and a power supply. A logic circuit, comprising: a system reset terminal to which a system reset signal for resetting the first logic block and the second logic block is applied when turned on.