JP2007286859A - Control unit and image forming device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent hindrance for a response to the outside caused by the reset of an I/O controller for coping with runaway while preventing the repetition of the runaway of the I/O controller including a sub CPU which releases energy saving by an outside access response. <P>SOLUTION: In a control unit including a main controller performing the control of a device 1 and an I/O controller controlling communication between the main controller and outside equipment or a network, the I/O controller is provided with communication means 22 and 25 which perform communication with the outside, a sub CPU which deals with outside access at energy saving in which operation voltages to the device and the main controller are cut and performs return to normal mode impressing operation voltages to the device and the main controller in replying the access, means 32 to 34 which detect abnormalities, and a means 36 which resets a reset permission element in the I/O controller except the sub CPU and the communication means 22 and 25 in responding to abnormality detection. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention includes, for example, a control device including a main controller including a main CPU that controls devices such as an image processing engine, and an I / O controller that includes a sub CPU that returns from the energy saving mode to the normal mode and communicates with the outside. The present invention also relates to an image forming apparatus using the same. The image forming apparatus can be used, for example, in a multi-function image processing apparatus represented by an MFP (Multi Function Peripheral) connected to a personal computer (PC).

JP-A-5-189393, JP 2002-278409 A, and Japanese Patent No. 3357514.

  In Patent Document 1, various reset signals are given to the reset processing circuit via a nonvolatile backup backup processing circuit built into the RAM between the CPU and the peripheral circuit, and the input reset signal is input to the RAM. A reset circuit that converts the stored reset signal type information and outputs it from the reset processing circuit to initialize a part or all of the peripheral circuits, or resets software parameters on the CPU 11 is described. Has been.

  Conventionally, in an image forming apparatus having a plurality of CPUs, it is well known that each processor detects an abnormality of each processor by monitoring each other (for example, Patent Document 2). In general, a watchdog timer is prepared for each processor, and when one of them detects an abnormal state, an initialization reset is applied to a circuit having all the remaining processors. This is very effective in the invention of a fixing device having a fixing heater or the like, but is not an effective means in an image forming apparatus having other uses because it is unnecessarily reset.

  In the cited document 3, various types of runaway of the sequence control CPU of the copying machine are detected, the runaway information is held in the memory, and when a new runaway is detected, the contents, the runaway information in the memory, and the operation state of the copying machine are displayed. A runaway detection return method is described in which runaway is evaluated accordingly and the copying machine is automatically returned or operation control is stopped according to the evaluation.

  By the way, in an image forming apparatus equipped with an I / O controller including an energy-saving CPU, it is known that a circuit other than the I / O controller is in a standby state or shuts down with a minimum power consumption in order to realize low power consumption. ing. In such a system, in order for the I / O controller to respond to access from the outside instead of the main controller, at least a circuit that responds to access from outside should be in a state where it can always respond to accept network packets and the like. I have to leave. In addition, initialization reset may be performed due to runaway of the CPU that is the control means of the I / O controller, but runaway due to a bug in the program may enter the same routine again even if rebooted, and repeatedly run away. is there.

  The present invention solves the above-mentioned problem, and has as its first object to prevent repetitive runaway of an I / O controller including a control means for releasing an energy saving mode in response to an external access, A second object is to prevent the external response from being hindered by a reset in the I / O controller corresponding to runaway.

(1) main control means (3) for controlling the device (1), and I / O control means (4) for controlling communication between the main control means (3) and an external device or a network In the control device,
The I / O control means (4) copes with external access in the energy saving mode in which the operating voltage to the communication means (22, 25), the device and the main control means for performing communication with the outside is cut off, and Sub-control means (21) for returning to the normal mode for applying an operating voltage to the device and the main control means in response to the access, an abnormality detection means (32-34) for detecting an abnormality of the sub-control means, And a reset means (36) for resetting the sub-control means and reset permission elements in the I / O control means excluding the communication means (22, 25) in response to the detection of the abnormality. Control device characterized.

  In addition, in order to make an understanding easy, the code | symbol of the response | compatibility or the equivalent element of the Example shown in drawing and mentioned later in parentheses was added for reference as an example.

  Thereby, when reset is asserted to the I / O control means (4) due to the runaway of the sub-control means (21) of the I / O control means (4), the network I / F (22), USB I / F (25), etc. that always respond to the outside are not reset and other resets that do not have an adverse effect on the system Perform a reset. As a result, abnormal operation of the control device can be prevented, and processing can be continued for external requests being processed.

  (2) The abnormality detection means (32 to 34) includes a storage medium (34) whose information is not cleared by the reset, and records information indicating that the abnormality is detected in the storage medium (34). The control device according to (1) above.

  For example, in order to prevent repeated runaway due to a bug in the program, if an abnormality is detected, such as a watchdog timer timeout, a storage medium that is not affected by the reset built in the I / O controller To record. Thereby, even after resetting, the fact that an abnormality has been detected is continuously held in the storage medium.

  (3) The control device according to (2), wherein the I / O control means (4) has means (36, 37) for notifying the reset to the main control means (3). In an embodiment to be described later, notification is made on the PCIINT signal line of the PCI bus between the main controller 3 and the I / O controller 4. Thereby, the main control means (3) can recognize the reset of the I / O controller 4.

  (4) The control device according to (3), wherein the main control means (3) integrates the number of resets and rewrites the boot program of the sub-control means (21) when the integrated value reaches a set value. .

  For example, when the main CPU of the main control means that returns to the operating state by canceling the energy saving mode refers to this information and the runaway of the sub CPU 21 of the I / O control means does not stop, the boot program for the sub CPU 21 Is rewritten and rebooted to stop the runaway of the sub CPU 21.

  (5) The control device according to any one of (1) to (4), wherein the communication unit (22, 25) receives an external access request even during the reset. According to this, troubles for external access are reduced.

  (6) The control device according to any one of (1) to (5), further including means (15) for notifying that the reset is being performed. Thereby, it is possible to inform the outside that the sub CPU 21 is in an abnormal state.

  (7) The reset unit (36) receives the reset request from the outside in preference to the reset request in response to the abnormality detection, and resets the communication unit (22, 25). Thru | or the control apparatus as described in any one of (5). Thereby, an external reset having a high priority can be accepted even during reset due to abnormality detection.

  (8) An image forming apparatus including the control device according to any one of (1) to (7), wherein the device (1) includes a plotter (6) that forms an image on a sheet.

  Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the drawings.

  FIG. 1 shows an outline of a digital copying machine MF1 having an MFP (Multi Function Printer) function according to an embodiment of the present invention. The copying machine MF1 includes a scanner 5 that reads an image on a document, a plotter 6 that writes an image on a sheet, and an engine unit 1 that includes an engine ASIC (Application Specific IC) 7 that controls the engine. The engine ASIC 7 is a copying machine. The main controller 2 that performs system control and image processing control is connected to a general-purpose bus such as a PCI bus.

  The main controller unit 2 includes an image memory 11 for accumulating image data, a local storage 10 for accumulating a large amount of image data and a job history, and IEEE1284 for transferring data using a plurality of signal lines simultaneously. There is a main controller ASIC 9 that controls each device including these and a main CPU 8 that controls the entire controller.

The I / O controller 4 of the copying machine MF1 is a general-purpose bus such as a PCI bus different from the general-purpose bus on the engine 1 side, and is connected to the main controller 3. The I / O controller 4 includes a network or USB host. An I / O controller ASIC 12 that controls I / O devices such as I / F, I ² C, SD, and operation unit 15, and a shared RAM 35 (FIG. 5) that can be accessed by both the main controller 3 and the I / O controller 12. The I / O controller ASIC 12 incorporates an energy-saving processor (sub CPU) 21 (FIGS. 2 to 5) that can control the main controller 3. A controller unit 2 including a main controller 3 and an I / O controller 4 performs overall control of the copying system, that is, system control. The main controller 3 is configured to easily access the internal RAM and the like in the I / O controller 4 including the shared RAM 35 (FIG. 5).

  The operation voltage is applied to the entire copying machine MF1, and it is possible not only to cope with external access but also to start image processing instructed in response to instructions such as reading, copying, printing, etc., that is, image processing instructions. The state that can be performed is referred to as a normal mode or an operation mode, and a circuit portion and a state for recognizing an external access (external access) such as communication from outside and a print instruction or an operator's operation (operator access) to the copying machine MF1 A state where power is always supplied only to a circuit that holds information and no power is supplied to other circuit portions is referred to as an energy saving mode (energy saving mode) or a power saving mode (low power mode).

  In the normal mode, when the standby state in which there is neither external access nor operator access continues for the set time or longer, the main CPU 8 instructs the power supply controller of the power supply circuit (not shown) to shift to the energy saving mode, and in response to this, the power supply The controller cuts off (turns off) the power supply circuit to the other circuit portions. As a result, the copying machine MF1 enters the energy saving mode, and in this embodiment, power supply to the engine unit 1 and the main controller 3 is stopped. However, the I / O controller 4 continues to be fed. In this energy saving mode, if there is external access or operator access, in response to this, the sub CPU 21 of the I / O controller 4 instructs the power supply controller to return to the normal mode, and in response to this, the power supply controller shuts off. Turn on the current feeding circuit. As a result, the copying machine MF1 enters the normal mode.

  FIG. 2 shows a route of communication information of the network response of the copying machine MF1 in the normal mode, and FIG. 3 shows a route of communication information of the network response in the energy saving mode. The controller unit 2 powers off the engine unit 1 and the main controller 3 in the energy saving mode, and is a sub CPU 21 built in the I / O controller 4, and is externally performed by the main CPU 8 in the normal mode (FIG. 2). Instead of handling the request (external access) in the energy saving mode, the overall power consumption of the system is reduced. In the energy saving mode, if there is a response from an external network or a response from a USB connection device, the main controller 3 is in Power Off and cannot accept the request. The sub CPU 21 built in the I / O controller 4 having the I / O device driver already mounted performs processing for an external request instead (FIG. 3).

  FIG. 4 shows details of the packet response of the I / O controller 4 when the main controller 3 is in the energy saving mode. When a specific external request (external access) such as reception of a packet is transmitted to the I / O controller 4, an interrupt signal is transmitted to the main controller 3 via the PCI bus as a return factor from the energy saving mode to the normal mode. . As a specific example, when packet data is sent from the outside in the energy saving mode, the sub CPU 21 performs appropriate processing on all received packets. Further, the sub CPU 21 instructs the power supply controller to return to the normal mode, and powers on the main controller 3 side and the engine 1 side. Then, the main controller 3 is notified as an interrupt signal that a packet response process, which is a factor for returning from the energy saving mode to the normal mode, has come.

  The main controller 3 that has returned to the normal mode before shifting to the energy saving mode due to Power On knows what the return factor has occurred by referring to the register in the I / O controller 4 after receiving the interrupt signal. The processing performed by the / O controller 4 is taken over and the processing is continued on the main controller 3 side. By performing such a series of operations, the power consumption of the entire system is reduced while accurately responding to external requests.

  FIG. 5 shows a signal route for runaway detection / reset by the watchdog timer 32 in the I / O controller ASIC 12. The ASIC 12 of the I / O controller 4 includes a watchdog (hereinafter abbreviated as WDG) timer 32, and the sub CPU 21 periodically writes data to a writable area in the WDG timer 32. The WDG timer 32 is informed that the sub CPU 21 is operating normally. If no data is written to the WDG timer 32 even after a certain period of time, the WDG timer 32 determines that an abnormality has occurred in the sub CPU 21, notifies this to the system I / F 36 via the reset I / F 33, The system I / F 36 performs “proper initialization processing”.

  FIG. 6 shows a reset processing signal route between the sub CPU 21 and the WDG timer 32. When the WDG timer 32 times out, a reset request is given to the reset I / F 33, and in response to this, the reset I / F 33 gives a reset signal to the system I / F 36, thereby filling the sub CPU 21 and the dots on FIG. The circuit element represented by the block is reset. A PCIINT signal on the PCI bus between the main controller 3 and the I / O controller 4 transmits the reset of the sub CPU 21 from the I / O controller 4 to the main controller 3.

  The WDG timer 32 includes a log memory that records the occurrence of a reset due to a WDG timeout, that is, a log recording unit 34. The log recording unit 34 is configured by a non-volatile recording medium (semiconductor memory) in which information is not initialized by reset, and continuously holds the information unless the log is cleared by the sub CPU 21. Usually, the CPU (sub CPU 21) runs out of control due to a bug in a program executed by the CPU that makes it impossible to leave the loop processing. The runaway due to such a phenomenon is likely to run away repeatedly in the same loop process even after reset due to abnormality detection.

  When the log recording unit 34 is built in, the main controller 3 determines whether the I / O controller 4 has been reset due to a WDG timeout (runaway detection reset) or the power is turned on based on the presence / absence of time-out occurrence information in the log recording unit 34. It is possible to determine whether a reset has been applied (power-on reset). When the PCIINT signal on the PCI bus between the main controller 3 and the I / O controller 4 transmits the reset of the sub CPU 21 from the I / O controller 4 to the main controller 3, the main controller 3 generates a time-out in the log recording unit 34. Based on the presence / absence of information, the I / O controller 4 determines whether a reset has occurred due to a WDG timeout (runaway detection) or a power-on reset.

  Based on this determination, when timeout occurs (runaway detection), the number of WDG timeouts is accumulated (counted) on the main controller 3 side, and the accumulated value (count value) is recorded in the memory.

  While the sub CPU 21 is reset, the main controller 3 can access a non-volatile recording medium such as the ROM 13 in which a program used by the sub CPU 21 in the I / O controller 4 is stored, and the sub CPU 21 is being reset. The boot program can be rewritten.

  When the recorded integrated value exceeds the threshold value, the main controller 3 rewrites the operation program (on the RAM) of the sub CPU 21 to a bug-free program, and then releases the reset to the sub CPU 21 to cancel the sub CPU 21. Return to normal and initialize (clear) the integrated value. When the recorded integrated value is less than or equal to the threshold value, the main controller 3 cancels the reset to the sub CPU 21 without rewriting the operation program of the sub CPU 21. The sub CPU 21 that has been released from the reset boots (starts up), executes initialization, initializes (clears) the WDG timer 32, and also clears the time-out occurrence information of the log recording unit 34 built in the WDG timer 32.

  Here, the “proper initialization process” when the WDG timer 32 times out (runaway detection) will be described. “Proper initialization processing” here means that a reset signal is supplied only to a circuit that requires initialization in the I / O controller 4 corresponding to runaway detection (ie, the overfill block in FIG. 5). To do. As described above, the I / O controller 4 must always respond to an external request (external access) in the energy saving mode. If the sub CPU 21 runs out of control due to a program bug or the like, the sub CPU 21 cannot write data to the WDG timer 32, so that an initialization process due to a WDG timeout is started.

At this time, if all the circuits are reset, the network I / F 22 is reset if the I / O controller 4 performs processing that does not go through the sub CPU 21, for example, a hardware network response. Therefore, an abnormality occurs on the network. Further, in the embodiment, the I / O controller 4 is connected to the main controller 3 via the PCI bus. Similarly, if the PCI I / F 37 in the I / O controller 4 is initialized by the WDG timeout, the configuration of the PCI bus is reset. There is no means to know that the PCI I / F on the O controller 4 side has been reset. Therefore, if transfer is performed from the main controller 3 side to the I / O controller 4 side via the PCI bus, it may be returned as a bus error, or in the worst case, it may cause a hang-up on the bus. On the other hand, regarding a circuit that accesses a storage medium such as I ² C I / F 38, which does not need to respond to an external response, if the initialization process is performed, no problem occurs in the system. Even if the data transfer fails, it is only necessary to notify the transfer master side of the failure and transfer the data again. On the other hand, if the initialization process is not performed, the transfer may not end indefinitely and may cause a problem. Furthermore, it is necessary to interrupt the re-initialization for the reset from the outside during the re-initialization and cope with the external reset having a high priority. This is because an external reset generally occurs when an important system problem occurs.

  From the above viewpoints, in this embodiment, in the I / O controller ASIC 12, a circuit (white block in FIG. 5) that supplies a reset signal when the WDG timer 32 times out (the sub CPU 21 runs out of control) and a circuit that does not supply The circuit that does not supply the reset signal is configured to accept an access request from the outside and respond to it. The network I / F 22 and the USB I / F 25 that always respond to the outside are not reset, and other resets that do not adversely affect the system are reset.

  In addition, both the circuit that does not supply the reset signal and the circuit that supplies the reset signal execute the initialization process corresponding to the external reset even while the circuit that supplies the reset signal is reset, that is, even when the initialization reset due to the timeout of the WDG timer 32 is asserted. I tried to do it. That is, even when an initialization reset due to abnormality detection is being asserted, an external reset request is preferentially accepted. When there is a reset request from the outside, the System I / F 36 supplies a reset signal to both the circuit that does not supply the reset signal and the circuit that supplies the reset signal.

  In addition, when initialization processing by WDG timeout (runaway detection) is started on the I / O controller 4 side, the main controller 3 always times out the WDG timer 32 unless the I / O controller 4 side is also monitored. There is no means of noticing the implementation of the initialization process in the I / O controller 4 due to (abnormality detection). If the main controller 3 becomes a controller system that monitors this initialization process, the main CPU 8 processes accordingly, and the performance of the controller unit 2 deteriorates.

  Therefore, in this embodiment, the existing signal between the main controller 3 and the I / O controller 4 is used to reset the sub CPU 21 in the I / O controller 4 from the I / O controller 4 to the main controller 3 when the abnormality is detected. To prevent the main CPU 8 from degrading its performance. The existing signal is used in order to avoid useless addition of a dedicated signal. In this embodiment, the PCIINT signal line of the PCI bus between the main controller 3 and the I / O controller 4 is used. The reset of the sub CPU 21 is transmitted from the I / O controller 4 to the main controller 3. Specifically, the system I / F transmits the reset signal generated by the reset I / F 33 to the main controller 3 through the PCIINT signal line. In this embodiment, the PCI bus is used for the signal line. Even when the connection I / F between the main controller 3 and the I / O controller 4 is another general-purpose I / F, the I / F can be used. If one signal is used, the same processing can be performed.

  The operation board 15 (FIG. 1) is connected to the operation unit I / F 39 (FIG. 5) of the I / O controller 4 of this embodiment, and when the reset due to the WDG timeout (runaway detection) occurs. When the main controller 3 is in the energy saving mode, there is no means to know from the outside. Therefore, in this embodiment, simultaneously with the start of the initialization process in the I / O controller 4 due to the abnormality detection, a display indicating that the re-initialization process is being performed is performed on the operation board 15. This prevents external access requests (external access, operator access) that cannot be handled.

1 is a block diagram showing an outline of the configuration of a digital copying machine with multiple functions according to an embodiment of the present invention. FIG. FIG. 2 is a block diagram showing a route of communication information of a network response of the copying machine MF1 in the normal mode in the controller unit 2 shown in FIG. It is a block diagram which shows the route of the communication information of the network response at the time of the energy saving mode in the controller part 2 shown in FIG. It is a block diagram which shows the signal flow of the packet response of the I / O controller 4 in the energy saving mode in the controller part 2 shown in FIG. FIG. 2 is a block diagram showing a configuration of the I / O controller ASIC 12 shown in FIG. 1, in which a circuit portion to which a reset signal is given when the watchdog timer 32 times out is indicated by dots. FIG. 6 is a block diagram showing routes of a reset signal and a clear signal between the sub CPU 21 and the WDG timer 32 shown in FIG. 5.

Explanation of symbols

1: Engine part 2: Controller part

Claims (8)

In a control device including main control means for controlling equipment, and I / O control means for controlling communication between the main control means and external equipment or a network,
The I / O control means copes with an external access in an energy saving mode in which an operating voltage to the external communication means, the equipment and the main control means is cut off, and responds to the access with the equipment. And sub-control means for returning to the normal mode for applying an operating voltage to the main control means, an abnormality detection means for detecting an abnormality of the sub-control means, and the sub-control means in response to detection of the abnormality, A control device comprising: reset means for resetting reset permission elements in the I / O control means excluding the communication means.   The control apparatus according to claim 1, wherein the abnormality detection unit includes a storage medium whose information is not cleared by the reset, and records information indicating that the abnormality is detected in the storage medium.   The control apparatus according to claim 2, wherein the I / O control unit includes a unit that notifies the main control unit of the reset.   The control device according to claim 3, wherein the main control unit integrates the number of resets and rewrites a reboot program of the sub-control unit when the integrated value reaches a set value.   The control device according to claim 1, wherein the communication unit receives an access request from the outside even during the reset.   The control device according to claim 1, further comprising means for notifying that the reset is being performed.   The control device according to claim 1, wherein the reset unit preferentially accepts an external reset request and resets the communication unit even during the reset in response to the abnormality detection. . An image forming apparatus comprising the control device according to claim 1, wherein the device includes a plotter that forms an image on a sheet.

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