JP4820271B2 - Image processing apparatus and image processing method - Google Patents

Description

  The present invention relates to an image processing apparatus and an image processing method.

FIG. 5 is a configuration example showing a conventional example of an image forming apparatus as an image processing apparatus.
The image forming apparatus 100 includes a plurality of devices.
A CPU 101 is a central processing unit that controls the entire system of the image forming apparatus. The boot ROM 102 is a memory that stores a boot program that is executed first when the power is turned on. The RAM 105 is a work memory, and is a storage device into which device control programs and the like are loaded. The operation panel controller 106 is a device that controls the input device 107 and the display device 108. The input device 107 is a device such as a mouse or a keyboard. The display device 108 is a device that displays operation details and the like. The printer engine 109 is a device that outputs an image. The scanner 110 is a device that reads an image in a document. The network I / F 111 is a device for interfacing with other networks, and is a device that performs data communication with devices connected to the bus 112. The bus 112 is a transmission path for performing data communication between devices.
As described above, in the image forming apparatus, the boot ROM 102 is used to store the boot program.

FIG. 6 is a configuration example of a boot ROM used in the image forming apparatus shown in FIG.
A boot ROM 200 shown in FIG. 6 stores a boot program 210 and a control program 220. The boot program 210 is a program executed first by the CPU 101 shown in FIG. The control program 220 is a program for controlling devices that constitute the image forming apparatus.

Some image forming apparatuses of this type employ a STR (Suspend to Ram) mode. This STR mode is one of the forms of “suspend” that, for example, puts the computer in a sleep state to reduce power consumption. The current state is saved in the memory, and power is supplied to most devices such as the CPU and hard disk. In this mode, energy is saved by stopping (see, for example, Patent Documents 1 to 6).
JP 2005-269103 A JP-A-2005-278110 JP 2005-303978 A JP 2006-126987 A JP 2006-155391 A JP 2006-252482 A

  By the way, although the above-mentioned conventional technology has a sub CPU that operates even during the STR mode in addition to the main CPU, if the sub CPU goes out of control during the STR mode, the sensor power ON / OFF function in the STR mode. Or high-speed start-up control does not function properly, the sensor power supply in the STR mode is always turned on, which may reduce the energy-saving effect, or the engine-side correction function is normal due to the reboot operation from the STR mode. I sometimes did not work.

  Therefore, an object of the present invention is to provide an image processing apparatus and an image processing method that prevent a reduction in energy saving effect during the STR mode.

The invention according to claim 1 has an engine control unit and a controller control unit that controls the engine control unit, a NAND flash memory in which a main system program of the image processing apparatus is stored , and reference data at the time of rebooting a nonvolatile memory for storing the high-speed startup information used to operate the boot program when the power supply is turned on, a boot ROM for the basic program is stored, provided in the controller control unit, an error flag The error register to be held and the error flag in the error register are checked when the image processing apparatus is started up. Based on the check result, power supplies other than the sub CPU and some devices are turned off. STR mode sensor during STR mode to monitor print activation and return factor -Means for detecting the runaway of the sub CPU , which causes the ON / OFF function of the power supply and the high speed startup control to not function normally, the sensor power supply in the STR mode is always in the ON state, and reduces the energy saving effect , means for performing a return from the runaway, the engine fast startup information of up order up the engine control unit at a high speed an image processing apparatus having a means for storing in non-volatile memory, and during the reboot Means for detecting an error flag of the error register .

According to the first aspect of the present invention, during the STR mode, the engine fast start information for detecting whether the sub CPU has runaway, recovering from the runaway, and determining whether the correction operation of the optical system is necessary or not. Is stored in the non-volatile memory, so that the sensor power supply in the STR mode is always kept from being turned on, so that the energy saving effect during the STR mode can be prevented.

According to a second aspect of the present invention, in the first aspect of the invention, the time when the engine JOB ends of the engine control unit for outputting an image, the time when the STR mode is shifted, and the time when the reboot is stored in the nonvolatile memory. Means are provided.

According to the second aspect of the present invention, there is provided means for storing in the nonvolatile memory the time at the end of the engine job of the engine control unit that outputs the image, the time at the time of transition to the STR mode, and the time at the reboot. Abnormal history information can be stored.

The invention according to claim 3 is the invention according to claim 1 or 2 , further comprising means for displaying an error code, an error time, and abnormality history information of the sub CPU abnormality on the operation unit at the time of rebooting. To do.

According to the third aspect of the present invention, by providing means for displaying an error code, error time, and abnormality history information of the sub CPU abnormality on the operation unit at the time of rebooting, a system abnormality occurs in the user and restarting Can be notified.

Invention of claim 4, in the invention of any one of claims 1 to 3, an error code to the connected server or terminal to the network at the time of reboot, the means for notifying the error time, and abnormality history information It is characterized by having.

According to the invention described in claim 4, by providing means for notifying an error code, error time, and abnormality history information to a server or terminal connected to the network at the time of rebooting, the user or system administrator can It is possible to grasp that an abnormality has occurred and a restart has occurred.

The invention according to claim 5 includes an engine control unit and a controller control unit that controls the engine control unit , stores the main system program of the image processing apparatus in the NAND flash memory, and stores the information for high-speed startup. with sexual memory as reboot reference data, it operates as a boot program at the time of power-up, and stores the basic program in the boot ROM, and a error flag to the error register provided in the controller control unit And the error flag in the error register is checked when the image processing apparatus is started. Based on the result of the check , power supplies other than the sub CPU and some devices are turned off, and the sub CPU prints from the outside. during STR mode for monitoring the start and return factor, it detects the runaway of the sub CPU, the runaway And to recover al, the engine fast startup information for determining whether the correction operation of the optical system need not be stored in non-volatile memory, characterized that you detect an error flag of the error register when the reboot And

According to the fifth aspect of the invention, during the STR mode, the engine fast start information for detecting whether or not the sub CPU has runaway, recovering from the runaway, and determining whether or not a correction operation of the optical system is necessary. Is stored in the non-volatile memory, so that the sensor power supply in the STR mode is always kept from being turned on, so that the energy saving effect during the STR mode can be prevented.

  According to the present invention, during the STR mode, information on the engine fast start for detecting whether the sub CPU has runaway, recovering from the runaway, and determining whether the optical system needs to be corrected is stored in the nonvolatile memory. By storing the data in the STR mode, it is possible to avoid that the sensor power supply in the STR mode is always in the ON state, and thus it is possible to prevent the energy saving effect from being reduced during the STR mode.

Next, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing an embodiment of an image processing apparatus to which an image processing method according to the present invention is applied.
The image processing apparatus shown in FIG. 1 mainly includes an engine control unit 10, an operation unit 15, and a controller control unit 20.

  In the engine control unit 10, a scanner control unit 11 that reads a document image (not shown), a plotter control unit 12 that prints an image read by the scanner unit control 11, and prints image data transferred from the controller control unit 20, A PSU (Power Supply) that controls the power supply of this apparatus, including a peripheral device control unit 13 for feeding printing paper (not shown) and discharging printed printing paper, and the engine control unit 10 and the controller control unit 20 Unit) unit 14. 13a is a sensor.

  Here, in the STR mode, the power sources other than the sub CPU 32b and some devices are turned off, and the sub CPU 32b monitors external print activation and return factors. The ASIC provided with the sub CPU 32b performs control so that the supply of sensor power (press plate opening / closing sensor and document set sensor) and LED power can be periodically turned on / off in order to increase the energy saving effect during STR. The ASIC provided with the sub CPU 32b has a high speed start control signal for starting up the engine drive system at a high speed. If the sub CPU 32b runs out of control in this STR mode, the sensor power ON / OFF function in the STR mode is provided. If the sensor power supply in the STR mode is always on, the energy-saving effect will be reduced, and the engine-side correction function will be normal in the reboot operation from the STR mode. It is thought that it does not work.

  In this system, a means for detecting the runaway of the sub CPU 32b is provided, and the automatic recovery from the system abnormality can prevent the energy saving effect during the STR mode from being reduced. Further, in this system, the fast start information is stored in the non-volatile memory 33 and used as the reference data at the time of rebooting, so that the correction process of the engine control unit 10 is appropriately performed without losing the fast start data. The system starts normally.

  The controller control unit 20 includes a CPU (Central Processing Unit) 22, a North chip 24, a South chip 27, and an ASIC (Application Specific Integrated Circuit) 1 ( 32) and main devices such as ASIC2 (23).

  The CPU 22 is a CPU that controls the main system of the controller control unit 20, and is connected to the Northchip 24. The Northchip 24 is controlled among the Southchip 27, the DDR2 (memory) 25, and the ASIC 2 (23). The DDR2 (memory) 25 is used as a work area for an execution program and an area for processing image data. The boot ROM BootRom 26 stores a basic program for controlling the basic operation of the controller control unit 20, and operates as a boot program at power-on. The Southchip 27 has a main system management function, a BootRom control for controlling the BootRom 26, and a control function for controlling a USB (Universal Serial Bus) Host via the USB Host I / F 28.

The USB controller 29 is connected to a NAND flash (memory) 31 in which the main system program of this apparatus is stored. The ASIC 2 (23) communicates with the engine control unit 10 to check the status of each control unit and perform image data transfer control.
The ASIC 2 (23) is an ASIC that processes scan data from the engine control unit 10 and print data input via an external I / F (Option Board I / F 30), and compresses / decompresses image data. , Has the function of scaling.
The hard disk driver HDD 21 stores scan data from the engine control unit 10 and print data input via an external I / F described later after image processing by the ASIC 2 (23).

  The ASIC 1 (32) includes a sub CPU 32b, a watch dog (WD 32a), an RTC 34 having an RTC (Real Time Clock) function, and includes an EEPROM 35, a nonvolatile memory 33, a NOR FLASH (memory) 36, and an SD (Standard). Digital) is an ASIC that includes I / O control performed via an SD CARD I / F 37 for a card, USB Device I / F 38, and network PHY control. Connection to the network is made via the PHY 39 and Network I / F 40.

  The ASIC 1 (32) also has a function of performing communication control with the operation unit 15 and energy saving control with the engine control unit 10. The EEPROM 35 stores a MAC address, the nonvolatile memory 33 stores information such as a user code, and the NOR FLASH 36 stores a program for the sub CPU 32b. The SD is used as means for downloading and upgrading the program to the Boot Rom 26, NAND Flash 31 and NOR FLASH 36 in which each program of the controller control unit 20 is stored, or used as each application software and emulation software.

  This image processing apparatus has each energy saving mode, and has a standby mode, an engine OFF mode, an STR mode, and a controller OFF mode.

  The standby mode is a mode in which each operation (copy operation, scanner operation, print operation) can be performed immediately when both the engine control unit 10 and the controller control unit 20 are powered on.

  The engine OFF mode is a mode in which status state notification and the like can be exchanged between the present apparatus and an external device in a state where the power of the engine control unit 10 is OFF and the power of the controller control unit 20 is ON.

  The STR mode is connected via the USB device I / F 38 or the network I / F 40 with the engine control unit 10 turned off and the controller control unit 20 other than part of the power turned off. This is a low power mode in which a print request from an external device is accepted.

  That is, during the STR mode, the sensor 13a, part of the PSU unit 14, LED power key 15a, DDR2 (25), USB Controller 29, part of South Chip 27, NAND Flash 31, RTC 34, ASIC1 (32), nonvolatile memory 33, NOR FLASH 36, USB Device I / F 38, PHY 39, and Network I / F 40 only operate.

  The controller OFF mode is a state in which the power supply of the engine control unit 10 is OFF and the power supply other than the South chip 27 and the ASIC 1 (32) of the controller control unit 20 is OFF, which is a lower power mode than the STR mode. Then, the LED power key 15a provided in the operation unit 15, the SD card insertion, the pressure plate opening / closing, the original setting to the ADF (Auto Document Feeder), and the like return from the main energy saving.

A fast start signal SG3 is sent from the ASIC 1 (32) for determining whether or not the correction operation of the process system and the optical system of the engine control unit 10 is necessary in the sequence of returning from the energy saving mode.
Before the system of the controller control unit 20 is started, the necessity for the correction operation of the process system and the optical system can be determined by the high-speed activation signal SG3, and the correction operation can be started. That is, since the correction can be started earlier than the correction operation after the communication between the engine control unit 10 and the controller control unit 20 is established, the present apparatus can be returned from the energy saving state earlier.

  In this way, the fast start signal SG3 is sent during the return sequence from the STR mode. If the sub CPU 32b in the ASIC 1 (32) runs out of control during the STR mode, the return from the STR mode is resumed. Even if it is not possible or is restored, the reliability of the signal level for fast start-up may be impaired, and unnecessary correction operation of the process system or optical system can be performed or vice versa. There can be a situation that does not exist.

  In addition, the ASIC 1 (32) also has a function for periodically turning on / off the power supply to the sensor power supply for opening and closing the plate, the paper set sensor power supply to the ADF, and the LED power supply in order to further reduce the power during the STR mode. However, if the sub CPU 32b in the ASIC 1 (32) runs away for some reason during the STR mode, there is a possibility that the energy saving effect may be reduced.

  The fast start signal SG3 is a signal transmitted after determining whether the elapsed time from the job end time of the engine control unit 10 is longer or shorter than a set time. SG1 is an operation control signal, SG2 is a sub CPU reboot detection signal, and SG4 is an energy saving control signal.

The ASIC 1 (32) has a built-in WD function and monitors whether the sub CPU 32b is operating normally during the STR mode. When the sub CPU 32b runs out of control for some reason, the WD function is activated and an interrupt signal is generated to the South Chip 27. Then, a main reset of the main body occurs, and the main system of the controller control unit 20 is rebooted.

FIG. 2 shows a flow chart at the time of transition to the STR mode and during the STR mode in the image processing apparatus shown in FIG.
Job end time data is stored in the non-volatile memory 33 every time the engine control unit 10 finishes a job (step S10).

  Next, it is determined whether or not the engine control unit 10 and the controller control unit 20 can shift to STR (step S11). If the shift to STR is possible (step S11 / YES), the time data at the time of shifting to STR is stored in a nonvolatile memory. After storing in 33 (step S12), the process proceeds to STR (step S13). If the STR shift is not possible (step S11 / NO), the process waits.

  During the STR mode, the operation of the sub CPU 32b is monitored by the WD function (step S14). When the sub CPU 32b does not run away (step S14 / NO), the sub CPU 32b runs away (step S14 / YES), and when the error flag of the error register in the ASIC1 (32) is set, the sub CPU After the level of the boot detection signal SG2 is changed (Low → High: Step S15) and an interrupt signal is generated for the South Chip 27, a main reset of the main body occurs, and the main system of the controller control unit 20 is rebooted ( Step S16).

FIG. 3 is a flowchart for rebooting the image processing apparatus shown in FIG.
First, the sub CPU error register in the ASIC 1 (32) is accessed (reading the error flag register: step S20), and it is determined whether an error bit is set (whether there is an error flag) (step S21). When the error bit is not set (step S21 / NO), the sub CPU reboot detection signal (L) is detected (step S29), and it is determined whether the fast start control signal SG3 is asserted (step S30). If it is asserted (step S30 / YES), the process control / optical system correction operation of the engine control unit 10 is started.

  When the error bit is set (step S21 / YES), the sub CPU reboot detection signal (H) is detected (step S22), and the error bit of the sub CPU error register is cleared (step S23).

  When the error bit is cleared (step S23), the level of the sub CPU reboot detection signal SG2 changes simultaneously with the clear (High → Low: step S24).

  Next, the time data X is read from the nonvolatile memory 33 (step S25), and the elapsed time T from the end of the job to the present is calculated from the current time data Z and the time data X read from the RTC (step S26). Then, the set value set in advance with the operation unit 15 or the like is compared with the elapsed time T (step S27).

  When the elapsed time T is larger than the set value (step S27 / YES), the process control / optical system correction operation of the engine control unit 10 is performed (step S28), and when the elapsed time T is smaller than the set value (step S28). In step S27 / NO), the correction operation is not performed, and the reboot operation is completed.

Here, when the error bit is set (step S21 / YES), the error code, error time, and abnormality history information are displayed on the operation unit 15, rebooted due to a sub CPU abnormality, and this apparatus has started up. To be notified. If an error bit is set (step S21 / YES), an error code, error time, and abnormality history information are displayed on the external device via the network I / F 40 (see FIG. 4). Reboot to notify that this device has started up.
FIG. 4 is an example of abnormality history information in the image processing apparatus shown in FIG.

Action effect
In the STR mode, power supplies other than the sub CPU and some devices are turned off, and the sub CPU monitors the external print activation and return factors. An ASIC provided with a sub CPU performs control such that the supply of sensor power (press plate opening / closing sensor and document set sensor) and LED power can be periodically turned ON / OFF in order to increase the energy saving effect during STR. An ASIC equipped with a sub CPU has a high-speed start control signal for starting up the engine drive system at a high speed. If the sub CPU goes out of control in this STR mode, the sensor power ON / OFF function in the STR mode is provided. If the sensor power supply in the STR mode is always on, the energy saving effect may be reduced, or the engine side correction function will be restarted from the STR mode. May not work properly.

  In this system, means for detecting runaway of the sub CPU is provided, and by automatically recovering from the system abnormality, it is possible to prevent the energy saving effect from being reduced during the STR mode. Further, in this system, the information for fast startup is stored in the non-volatile memory and used as the reference data at the time of rebooting, so that the correction processing of the engine unit is appropriately performed without losing the data for fast startup, and the system Can be started normally.

By providing a means for detecting an error flag when rebooting, it is possible to determine whether started with the or normal return and power-started at reboot.

By providing a means for determining whether to perform the correction operation of the engine section, when the correction operation is not required rises at a high speed startup mode, correction processing of the engine unit performs properly if needed corrective action be able to.

The engine JOB history information of the end time and the time and reboot the time when STR migration by providing a means for storing in non-volatile memory can store error history information.

By providing means for displaying on the operation unit of this apparatus, it is possible to notify the user that a system abnormality has occurred and a restart has occurred.

By providing a means for notifying a server or terminal connected to the network via the network I / F of this device, the user or system administrator is notified that a system failure has occurred and a restart has occurred. be able to.

  The above-described embodiment shows an example of a preferred embodiment of the present invention, and the present invention is not limited thereto, and various modifications can be made without departing from the scope of the invention. is there.

1 is a block diagram showing an embodiment of an image processing apparatus to which an image processing method according to the present invention is applied. FIG. 2 is a flowchart when the STR mode shifts and during the STR mode in the image processing apparatus shown in FIG. 1. FIG. 2 is a flowchart for rebooting the image processing apparatus illustrated in FIG. 1. 3 is an example of abnormality history information in the image processing apparatus shown in FIG. 1. 1 is a configuration example showing a conventional example of an image forming apparatus as an image processing apparatus. 6 is a configuration example of a boot ROM used in the image forming apparatus shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Engine control part 11 Scanner control part 12 Plotter control part 13 Peripheral machine control part 13a Sensor 14 PSU part 15 Operation part 15a LED power key 20 Controller control part 21 HDD
22 CPU
23 ASIC2
24 North Chip
25 DDR2
26 Boot Rom
27 South Chip
28 USB Host I / F
29 USB Controller
30 Option Board I / F
31 NAND Flash
32 ASIC1
33 Nonvolatile memory 34 RTC
35 EEPROM
36 NOR FLASH
37 SD CARD I / F
38 USB Device I / F
39 PHY
40 Network I / F

Claims (5)

A NAND flash memory storing a main system program of an image processing apparatus having an engine control unit and a controller control unit for controlling the engine control unit ;
A non-volatile memory for storing information for fast startup used as reference data at reboot ;
To act as a boot program at the time of power-up, and a boot ROM that basic program is stored,
An error register provided in the controller control unit and holding an error flag;
The error flag in the error register is checked when the image processing apparatus is started up, and the power other than the sub CPU and some devices is turned off based on the check result. During the STR mode, the ON / OFF function of the sensor power supply in the STR mode and the high-speed start-up control will not function normally, and the sensor power supply in the STR mode will always be in the ON state, which will reduce the energy saving effect and means for detecting the runaway of the sub CPU,
Means for returning from the runaway;
Wherein the engine fast startup information of up order up the engine control unit at a high speed an image processing apparatus having a means for storing in non-volatile memory, and means for detecting an error flag of the error register when the reboot And an image processing apparatus. The image processing according to claim 1, further comprising a means for storing the time when time and reboot when the engine JOB end time and STR mode transition of the engine control unit for outputting an image in the non-volatile memory apparatus. Reboot error code on the operation unit at the time, the error time, and the image processing apparatus according to claim 1, wherein further comprising means for displaying the abnormality history information of the sub-CPU error. Reboot connected error code to the server and the terminal to the network at the time, the error time, and the image processing apparatus according to any one of claims 1 to 3, further comprising a means for notifying the abnormality history information. A main system program of an image processing apparatus having an engine control unit and a controller control unit for controlling the engine control unit is stored in a NAND flash memory ;
Use nonvolatile memory that stores information for fast startup as reference data at reboot ,
To act as a boot program of when the power supply is turned on, and stores the basic program in the boot ROM,
Holding an error flag in an error register provided in the controller control unit;
An error flag in the error register is checked when the image processing apparatus is started up. Based on the check result, power supplies other than the sub CPU and some devices are turned off, and the sub CPU starts or returns printing from the outside. During the STR mode to monitor the cause, the runaway of the sub CPU is detected,
Perform recovery from the runaway,
The engine fast startup information for determining whether it is necessary to correct the operation of the optical system is stored in the nonvolatile memory, an image processing method characterized that you detect an error flag of the error register when the reboot.

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