JP2011079176A - Controller for image processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology for appropriately achieving both power saving and high speed of an image processor. <P>SOLUTION: A controller for the image processor having a function of switching a plurality of operation modes includes a CPU limited in power on/off frequency; a sub-CPU for controlling switching from a power-saving mode to a normal mode, and other devices. In any power-saving mode, the CPU is set into a sleep state, and the sub-CPU is set into an ON state of being capable of carrying out usual functions. The other devices are set into the sleep state or power-off state. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an image processing apparatus such as a printer, a copier, a multifunction peripheral, and a scanner, and a controller for the image processing apparatus. The present invention particularly relates to an image processing apparatus and a power saving technique for a controller for the image processing apparatus.

  The image processing apparatus has a normal mode in which functions of the image processing apparatus such as printing and copying can be executed, and a mode in which power consumption is smaller than that mode (hereinafter referred to as “power saving mode”). There is. In the power saving mode, power supply to some devices (for example, a print engine, CPU, HDD, DRAM, etc.) in the image processing device is turned off, or some devices are set to a sleep state. The power consumption can be suppressed to be smaller than that in the normal mode.

  For example, Patent Document 1 describes an image forming apparatus that turns off the power of an HDD when shifting to a power saving mode.

JP 2008-55633 A

  Incidentally, in recent years, image processing apparatuses are required to further reduce power consumption, and further, it is required to increase the processing speed.

  However, various problems arise when trying to achieve both power saving and high-speed processing. For example, when a CPU with a higher processing speed is used, power consumption tends to increase. In addition, a CPU with a higher processing speed may have a limited number of times of power ON / OFF from the viewpoint of reliability and operation guarantee. If the power of the CPU is turned off in the power saving mode, the reliability decreases. There is a risk.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a technique for more appropriately balancing power saving and speeding up of an image processing apparatus.

  A first aspect of the present invention for solving the above problems is a controller for an image processing apparatus having a function of switching between a plurality of operation modes, which is connected to a CPU having a power ON / OFF limit and a CPU A first mode ASIC, a second ASIC connected to the first ASIC, a sub CPU provided in the second ASIC, and other devices. A first power saving mode that consumes less power than a mode, and a second power saving mode that consumes less power than the first power saving mode. In the normal mode, the CPU and the The first ASIC, the second ASIC, and the other devices are in an ON state capable of executing their normal functions, and the sub CPU consumes less power than the ON state. In the first power saving mode, the CPU is in a sleep state, and at least one of the first ASIC, the second ASIC, and the other device is in a sleep state, The sub CPU is in an ON state, and in the second power saving mode, the CPU is in a sleep state, at least one of the first ASIC and the other device is in a power OFF state, and the second CPU The ASIC is in a sleep state, and the sub CPU is in an ON state.

  Here, in the controller for the image processing device, the sub CPU transmits a reset signal to the CPU when switching from the second power saving mode to the normal mode. Also good.

  The controller for any one of the image processing apparatuses described above, wherein the CPU and the first ASIC are connected by a signal line for inputting an interrupt signal to the CPU. The input terminal may be pulled up.

  The controller for any one of the image processing apparatuses described above, wherein the CPU controls switching from the normal mode to the first power saving mode, and the sub CPU starts from the first power saving mode. Controlling switching to the normal mode, switching from the first power saving mode to the second power saving mode, and switching from the second power saving mode to the normal mode. It may be.

  A second aspect of the present invention for solving the above problem is a controller for an image processing apparatus having a function of switching between a plurality of operation modes, a CPU having a limited number of power ON / OFF, a sub CPU, And other devices, a normal mode, a first power-saving mode that consumes less power than the normal mode, and a second power-saving mode that consumes less power than the first power-saving mode In the normal mode, the CPU and the other devices are in an ON state capable of executing their normal functions, and the sub CPU is in a sleep state in which power consumption is smaller than that in the ON state. In the first power saving mode, the CPU is in a sleep state, at least one of the other devices is in a sleep state, and the sub CPU is in an O state. In the second power saving mode, the CPU is in a sleep state, at least one of the other devices is in a power OFF state, and the sub CPU is in an ON state. .

  A third aspect of the present invention for solving the above problem is a printer, a scanner, a copier, or a multifunction machine on which any one of the above-described controllers for the image processing apparatus is mounted.

1 is a diagram illustrating a schematic configuration of a printer controller 1 according to an embodiment of the present invention. 2 is a diagram illustrating an example of an operation mode of the printer controller. FIG. FIG. 6 is a flowchart showing transition processing of various operation modes in the printer controller.

  Hereinafter, an embodiment of the present invention will be described.

  FIG. 1 is a block diagram illustrating a schematic configuration of a printer controller 1 according to an embodiment of the present invention. In the present embodiment, a printer will be described as an example of an image processing apparatus, and a printer controller will be described as an example of a controller. Of course, the image processing apparatus is not limited to a printer, and may be a copier, a multifunction peripheral, a scanner, or the like.

  The printer controller 1 is mounted on a printer (not shown) and controls the printer in an integrated manner to realize various functions of the printer. As will be described later with reference to FIGS. 2 and 3, the printer controller 1 has a plurality of operation modes and performs power control according to each mode. The printer is, for example, an ink jet printer or a laser printer.

  The printer controller 1 includes a CPU 10, an ASIC (Application Specific Integrated Circuit) 20, a RAM 30, an ASIC 40, a ROM 50, an NVRAM (Non-Volatile RAM) 60, a network interface (I / F) 70, and switch circuits 80 to 82. The ASIC 40 has a sub CPU 41.

  The CPU 10 is a main arithmetic unit that controls the printer controller 1 and the entire printer. In the present embodiment, the CPU 10 defines the upper limit value of the number of power ON / OFF times that guarantees reliability and operation as a specification. Further, the CPU 10 has a sleep mode that consumes less power than the normal operation mode.

  As will be described later with reference to FIGS. 2 and 3, the CPU 10 performs control for causing the printer controller 1 to transition from the normal mode to the power saving mode.

  The ASIC 20 (ASIC 1) includes a CPU interface, a memory interface, an interface connected to the ASIC 40, an image processing circuit, and the like, and executes access control to the RAM 30, image processing for generating print data to be sent to the printer engine, and the like. It is. The ASIC 20 has a sleep mode in which the power consumption of at least some of the devices (eg, memory, processing circuit, etc.) on the ASIC 20 is smaller than the normal operation mode.

  The ASIC 20 is connected to the CPU 10 via a signal line 21 for transmitting an interrupt signal (wake-up signal) for requesting a wake-up process to the CPU 10. The input terminal of the signal line 21 of the CPU 10 is pulled up to stabilize the potential when the power of the ASIC 20 is turned off. The wake-up process is a process for the CPU 10 (the program executed by the CPU 10) to return to the state immediately before the transition to the sleep mode.

  The RAM 30 is a volatile memory that temporarily stores programs executed by the CPU 10, image data to be processed, and the like. The RAM 30 is, for example, a DDR-SDRAM. The RAM 30 has a sleep mode (for example, self-refresh mode) that consumes less power than the normal operation mode, and a mode (for example, power-down mode) in which the power consumption is further reduced by stopping the internal clock.

  The ASIC 40 (ASIC2) is a device that executes control of various input / output (I / O) devices and I / F devices such as the ROM 50, the NVRAM 60, the network I / F 70, the operation panel, and the printer engine. The ASIC 40 has a sleep mode in which the power consumption of at least some of the devices (eg, memory, processing circuit, etc.) on the ASIC 40 is smaller than that in the normal operation mode. The ASIC 40, for example, transfers information output from the I / O device or I / F device to the CPU 10 or the RAM 30, or transfers information transmitted from the CPU 10 to various I / O devices or I / F devices. To do.

  The ASIC 40 is connected to the CPU 10 through a signal line 42 for transmitting a reset signal for requesting the CPU 10 to perform a reset process. The reset process is a process for the CPU 10 (a program executed by the CPU 10) to return to an initial state by resetting a program counter or the like, for example. The ASIC 40 is connected to each of the switch circuits 80 to 82 by a signal line 43 for transmitting a signal for switching each of the switch circuits 80 to 82 to ON or OFF.

  The sub CPU 41 is an arithmetic device that performs control to change the operation mode of the printer controller 1. As will be described later with reference to FIGS. 2 and 3, the sub CPU 41 performs control for causing the printer controller 1 to transition from the power saving mode to another different power saving mode, and control for causing the printer controller 1 to transition from the power saving mode to the normal mode. Do.

  Further, the sub CPU 41 has a sleep mode in which power consumption is lower than that in the normal operation mode. Since the sub CPU 41 mainly performs processing related to the transition of the operation mode, the sub CPU 41 does not need to have high speed and high function as compared with the CPU 10.

  The ROM 50 and the NVRAM 60 are non-volatile memories that store programs and setting data that should be retained continuously even when the printer is turned off. The ROM 50 is, for example, a flash ROM. The NVRAM 60 is a circuit having a small battery and an SRAM, for example.

  The network I / F 70 is a device that communicates with an external device (for example, a computer in which a printer driver program is installed) via a network.

  The switch circuit 80 is controlled by the sub CPU 41 via the signal line 43 and turns on or off the power supply to the ROM 50 and the NVRAM 60. The switch circuit 81 is controlled by the sub CPU 41 via the signal line 43 and turns on or off the power supply to the ASIC 20. The switch circuit 82 is controlled by the sub CPU 41 via the signal line 43, and turns on or off the power supply to the RAM 30.

  The general configuration of the printer controller 1 has been described above. However, the main configuration has been described in describing the features of the present invention, and is not limited to the above configuration. Further, other configurations included in a general image reading apparatus are not excluded.

  For example, the switch circuits 80 to 82 may be included in the ASIC 40. The network I / F 70 may be separate from the printer controller 1. The ROM 50 and the NVRAM 60 may be connected to the ASIC 20 respectively. The printer engine may be connected to the ASIC 20. The ASIC 40 may be connected to devices such as a USB I / F, a serial I / F, and an HDD. Further, the ASIC 20 and the ASIC 40 may be integrated.

  Next, various operation modes implemented in the printer controller 1 and transition control between the various modes will be described.

  FIG. 2 is a diagram illustrating an example of the operation mode of the printer controller 1.

  The printer controller 1 has three modes (“normal mode (mode 0)”, “power saving mode 1 (mode 1)”, and “power saving mode 2 (mode 2)”).

  “ON” indicates a state in which power is supplied to the device and various normal functions of the device can be executed. “Sleep” indicates a state in which power is supplied to the apparatus but the sleep mode is being executed. “Partial Sleep” indicates that at least a part of the ASIC 20 or the ASIC 40 or at least one of the other devices (RAM 30, ROM 50, NVRAM 60) is executing the sleep mode. “OFF” indicates a state where the supply of power to the apparatus is interrupted.

  In the “normal mode (mode 0)”, CPU 10 = ON, ASIC 20 = ON, ASIC 40 = ON, sub CPU 41 = Sleep (or ON), and other devices = ON.

  In “power saving mode 1 (mode 1)”, CPU10 = Sleep, ASIC20 = partial sleep, ASIC40 = partial sleep, sub CPU41 = ON (or sleep), and other devices = partial sleep.

  In the case of the power saving mode 1, at least one of the network I / F 70, the operation panel, and the printer engine may be shifted to the sleep mode. However, in the sleep mode, the network I / F 70 monitors at least reception of predetermined data (for example, print data) that should cause the CPU 10 to operate in the normal mode, and transfers the data to the sub CPU 41 when the predetermined data is received. . Similarly, the operation panel also monitors at least a predetermined user operation (for example, an operation of a button for canceling the power saving mode) for operating the CPU 10 in the normal mode, and notifies the sub CPU 41 when the operation is detected. .

  In “power saving mode 2 (mode 2)”, CPU 10 = Sleep, ASIC 20 = OFF, ASIC 40 = partial Sleep, sub CPU 41 = ON (or Sleep), and other devices = OFF (or Sleep).

  Note that in the power saving mode 2, at least one of the network I / F 70, the operation panel, and the printer engine may transition to a mode that consumes less power than the sleep mode, or to a power-off state. However, the network I / F 70 monitors at least reception of predetermined data that should cause the CPU 10 to operate in the normal mode, and transfers the data to the sub CPU 41 when the predetermined data is received. Similarly, the operation panel monitors at least the operation of a predetermined user who should operate the CPU 10 in the normal mode, and notifies the sub CPU 41 when the operation is detected.

  In the plurality of modes described above, combinations of modes that can be changed are mode 0-> mode 1, mode 1-> mode 0, mode 1-> mode 2, and mode 2-> mode 0.

  As described above, in the present embodiment, in the power saving mode 1 and the power saving mode 2, the CPU 10 is set in the sleep mode and the power is not turned off. Therefore, in any mode, the increase in the number of times of power ON / OFF of the CPU 10 is limited as much as possible, and the reliability can be kept high for a longer period. In the present embodiment, in the power saving mode 2, power is turned off for some devices other than the CPU 10. Therefore, further power saving can be achieved while extending the life of the CPU 10.

  In the power saving mode 2, among the devices other than the CPU 10, devices that are likely to be deteriorated in reliability due to an increase in the number of power ON / OFF times may be set to the sleep mode. In this way, the reliability of the entire controller can be kept high for a longer period.

  FIG. 3 is a flowchart showing transition processing of various operation modes in the printer controller 1. This flow is executed in the normal mode (mode 0) after the printer is turned on and started.

  In S1, the CPU 10 monitors whether or not a predetermined time has elapsed since the start of the normal mode (mode 0). Specifically, the CPU 10 uses a timer to determine whether or not a predetermined time (for example, 15 minutes) has elapsed since the last reception of an instruction for processing that requires processing by the CPU 10 (for example, processing related to printing). Monitor. When the predetermined time has not elapsed (S1: NO), the CPU 10 continues monitoring. When the predetermined time has elapsed (S1: YES), the CPU 10 advances the process to S2.

  Note that the monitoring condition is not limited to the above, and the CPU 10 may monitor, for example, whether or not a user operation for setting the power saving mode 1 has been received via the operation panel.

  In S2, the CPU 10 performs a process of transitioning from the normal mode (mode 0) to the power saving mode 1 (mode 1). Specifically, the CPU 10 requests the ASIC 20 and the ASIC 40 to shift to the sleep mode (partial sleep). Further, the RAM 30 is requested to shift to the sleep mode. Then, after the ASIC 20, the ASIC 40, and the RAM 30 transition to the sleep mode, the CPU 10 itself also transitions to the sleep mode, and the process proceeds to S3.

  Here, when the ASIC 20 shifts to the sleep mode, the ASIC 20 stops the function of transmitting the interrupt signal so as not to transmit the interrupt signal to the CPU 10. Further, when the ASIC 40 shifts to the sleep mode, the ASIC 40 returns the sub CPU 41 from the sleep mode to the ON state.

  In S3, the sub CPU 41 monitors whether predetermined data has been received. Specifically, the sub CPU 41 monitors whether or not at least predetermined data (for example, print data transferred from the network I / F 70) for operating the CPU 10 in the normal mode has been received. When the predetermined data is received (S3: YES), the sub CPU 41 advances the process to S4. If the predetermined data has not been received (S3: NO), the process proceeds to S5.

  Note that the monitoring condition is not limited to the above, and the sub CPU 41 may monitor, for example, whether or not the user's operation for setting the normal mode is accepted via the operation panel.

  In the above description, the sub CPU 41 performs monitoring in S3. However, at least one of the ASIC 20 and the ASIC 40 may perform monitoring. That is, at least one of the ASIC 20 and the ASIC 40 monitors a predetermined circuit in a portion that is not in the sleep mode. At this time, the sub CPU 41 may remain set in the sleep mode.

  In S4, the sub CPU 41 performs a process of transitioning from the power saving mode 1 (mode 1) to the normal mode (mode 0). Specifically, the sub CPU 41 requests the ASIC 20, the ASIC 40, and the RAM 30 to shift to the ON state. After the ASIC 20, ASIC 40, and RAM 30 transition to the ON state, the sub CPU 41 itself transitions to the sleep mode, and the process returns to S1.

  In addition, after ASIC20, ASIC40, and RAM30 change to ON state, ASIC20 transmits a wakeup signal to CPU10 and performs a wakeup process. The CPU 10 can return to the ON state and execute the program from the state immediately before the printer controller 1 shifts to the power saving mode 1. At this time, the CPU 10 may output information indicating that the power saving mode 1 has returned to the normal mode 0 to the operation panel.

  In S5, the sub CPU 41 monitors whether or not a predetermined time has elapsed since the power saving mode 1 (mode 1) was started. Specifically, the sub CPU 41 uses a timer to monitor whether or not a predetermined time (for example, 15 minutes) has elapsed since the transition from the mode 0 to the mode 1. If the predetermined time has not elapsed (S5: NO), the sub CPU 41 returns the process to S3. When the predetermined time has elapsed (S5: YES), the sub CPU 41 advances the process to S6.

  Note that the monitoring condition is not limited to the above, and the sub CPU 10 may monitor whether a user operation for setting the power saving mode 2 is received via the operation panel, for example.

  In S6, the sub CPU 41 performs a process of transitioning from the power saving mode 1 (mode 1) to the power saving mode 2 (mode 2). Specifically, the sub CPU 41 requests the ASIC 20, the RAM 30, the ROM 50, and the NVRAM 60 to shift to the power OFF state. The ASIC 20, the RAM 30, the ROM 50, and the NVRAM 60 perform various setting processes for shifting to the power OFF state. Thereafter, the sub CPU 41 transmits a signal for turning off the power to the switch circuits 80 to 82, and advances the processing to S7. Note that the ASIC 40 remains in the sleep mode (partly Sleep) because it is necessary to continue the processing by the sub CPU 41.

  In S7, the sub CPU 41 monitors whether predetermined data has been received. Specifically, the sub CPU 41 monitors whether or not at least predetermined data (for example, print data transferred from the network I / F 70) for operating the CPU 10 in the normal mode has been received. When the predetermined data is received (S7: YES), the sub CPU 41 advances the process to S8. If predetermined data has not been received (S7: NO), monitoring is continued.

  Note that the monitoring condition is not limited to the above, and the sub CPU 41 may monitor, for example, whether or not the user's operation for setting the normal mode is accepted via the operation panel.

  In S8, the sub CPU 41 performs a process of transitioning from the power saving mode 2 (mode 2) to the normal mode (mode 0). Specifically, the sub CPU 41 transmits a signal for turning on the power to the switch circuits 80 to 82 and requests the ASIC 40 to shift to the ON state. When the ASIC 20, the RAM 30, the ROM 50, and the NVRAM 60 are supplied with power, the ASIC 20, the RAM 30, the ROM 50, and the NVRAM 60 execute various activation processes and transition to the ON state. At this time, the ASIC 20 inhibits the wake-up signal from being sent to the CPU 10. In addition, the ASIC 40 also executes the startup process and transitions to the ON state. After the various devices transition to the ON state, the sub CPU 41 itself transitions to the sleep mode and returns the process to S1.

  Here, after the various devices transition to the ON state, the ASIC 40 transmits a reset signal to the CPU 10. The CPU 10 can return to the ON state and start processing from the reset state. At this time, the CPU 10 may output information indicating that the power saving mode 2 has returned to the normal mode 0 to the operation panel. In the case of resetting, since the CPU 10 executes the program from the initial state, it cannot be distinguished from the case where the power is turned off. Therefore, for example, the sub CPU 41 transmits a signal indicating that the power is restored from the power saving mode 2 to the CPU 10, and the CPU 10 determines that the power saving mode 2 is restored to the normal mode 0 based on the signal. You just have to do it.

  Each of the steps in FIG. 3 is divided according to main processing contents in order to facilitate understanding of the processing of the printer controller 1. The invention of the present application is not limited by the way of dividing steps and names. The processing of the printer controller 1 can be divided into more steps depending on the processing content. Moreover, it can also divide | segment so that one step may include many processes.

  The embodiment of the present invention has been described above. According to the present embodiment, it is possible to provide a technique for more appropriately balancing power saving and speeding up of the image processing apparatus.

  In other words, in this embodiment, even when a CPU (CPU with a higher processing speed) in which the number of times of ON / OFF is limited is adopted as the controller, the power is not turned off in the power saving mode. Thereby, the increase in the number of times the CPU is turned on / off is limited as much as possible, and the reliability of the operation of the CPU can be kept high for a longer period.

  In this embodiment, the CPU is not turned off in the power saving mode, but a more power saving mode (power saving mode 2) is provided in which the power of some devices other than the CPU is turned off. . Thereby, it is possible to further save power while extending the life of the CPU whose number of ON / OFF times is limited.

  In the present embodiment, a signal line connecting the ASIC (ASIC 20) for controlling access to the RAM and the CPU is pulled up 22. This prevents an erroneous wake-up signal from being input to the CPU when the ASIC is turned off, and prevents the CPU from waking up from the sleep mode.

  In the present embodiment, the ASIC (ASIC 20) that performs RAM access control does not transmit a wake-up signal to the CPU when returning from the power OFF state to the ON state. Instead, the sub CPU that controls the return from the power saving mode to the normal mode transmits a reset signal to the CPU. Thus, since the CPU can start executing the program from the initial state, the controller can operate normally even if the ASIC is initialized by turning on the power. If a wake-up signal is used, the state of the ASIC initialized by turning on the power and the state of the CPU (program) started from the sleep mode may not match, and the controller may hang up. .

  In this embodiment, the power saving mode (power saving mode 2) for turning off the power of some devices other than the CPU (ASIC 20, RAM 30, ASIC 40, ROM 50, NVRAM 60, etc.) Transition is not possible without going through the power saving mode (power saving mode 1) in which the device is set to sleep mode. As a result, various devices do not suddenly change from the power-on state to the power-off state, and the load on the device that is likely to be deteriorated in reliability due to an increase in the number of power on / off operations can be reduced. As a result, the reliability of the operation of the entire controller can be kept high for a longer period. In addition, the failure rate for a longer period can be reduced.

  Conventionally, there is a system having a power saving mode in which most devices including a CPU on a controller are turned off. However, in such a system, it is difficult to employ a CPU with a limited number of times of power ON / OFF. In addition, CPUs that have no restrictions or less restrictions than CPUs that have restrictions on the number of power ON / OFF cycles tend to be slower in processing speed or higher in price. The condition is not well balanced.

  Under the circumstances as described above, if the present invention is adopted, a CPU with a limited number of times of power ON / OFF can be used without turning off the power in the power saving mode. Further, the ASIC and other devices connected to the CPU can be turned off in the power saving mode. That is, if the present invention is employed, a high-speed and inexpensive CPU can be used for the controller, and the power consumption of the image processing apparatus and the controller can be reduced overall. Further, by using a high-speed CPU for the controller, it is possible to shorten the time during which the power consumption of the image processing apparatus is high (for example, print processing, copy processing, etc.), and to reduce overall power consumption. Thus, it is possible to achieve both power saving and high performance in a balanced manner.

  The above-described embodiments of the present invention are intended to illustrate the gist and scope of the present invention and are not intended to be limiting. Many alternatives, modifications, and variations will be apparent to those skilled in the art.

  For example, the printer controller 1 may be allowed to transition from the normal mode to the power saving mode 2 without going through the power saving mode 1. Moreover, the structure which has two modes, normal mode and the power saving mode 2, may be sufficient. Further, a mode may be provided between the power saving mode 1 and the power saving mode 2 that consumes less power than the power saving mode 1 and consumes more power than the power consumption mode 2.

  In addition, for example, the sub CPU 41 does not need to be in the ON state in the power saving mode 1 and the power saving mode 2, and is turned on when waiting in the sleep state and receiving predetermined data from the network I / F 70 or the operation panel. You may make it return to a state.

1: Printer controller, 10: CPU, 20: ASIC (ASIC1), 21: Signal line, 22: Pull-up, 30: RAM, 40: ASIC (ASIC2), 41: Sub CPU 41, 42: Signal line, 43: Signal Line, 50: ROM, 60: NVRAM, 70: Network I / F, 80-82: Switch circuit

Claims (6)

An image processing device controller having a function of switching between a plurality of operation modes,
A CPU with a limited number of times of power ON / OFF, a first ASIC connected to the CPU, a second ASIC connected to the first ASIC, and a sub CPU provided in the second ASIC , Other devices, and
A normal mode, a first power saving mode that consumes less power than the normal mode, and a second power saving mode that consumes less power than the first power saving mode,
In the normal mode,
The CPU, the first ASIC, the second ASIC, and the other devices are in an ON state capable of executing their normal functions, and the sub CPU is in a sleep state in which power consumption is smaller than that in the ON state. And
In the first power saving mode,
The CPU is in a sleep state, at least one of the first ASIC, the second ASIC, and the other devices is in a sleep state, and the sub CPU is in an ON state,
In the second power saving mode,
The CPU is in a sleep state, at least one of the first ASIC and the other devices is in a power OFF state, the second ASIC is in a sleep state, and the sub CPU is in an ON state.
A controller for an image processing apparatus. The controller for an image processing apparatus according to claim 1,
The sub CPU is
A reset signal is transmitted to the CPU upon switching from the second power saving mode to the normal mode;
A controller for an image processing apparatus. The controller for an image processing apparatus according to claim 1 or 2,
The CPU and the first ASIC are connected by a signal line for inputting an interrupt signal to the CPU,
The interrupt signal input terminal of the CPU is pulled up,
A controller for an image processing apparatus. The controller for an image processing apparatus according to any one of claims 1 to 3,
The CPU
Controlling switching from the normal mode to the first power saving mode;
The sub CPU is
Switching from the first power saving mode to the normal mode, switching from the first power saving mode to the second power saving mode, and switching from the second power saving mode to the normal mode Control,
A controller for an image processing apparatus. An image processing device controller having a function of switching between a plurality of operation modes,
It has a CPU with limited power ON / OFF count, a sub CPU, and other devices,
A normal mode, a first power saving mode that consumes less power than the normal mode, and a second power saving mode that consumes less power than the first power saving mode,
In the normal mode,
The CPU and the other devices are in an ON state in which each normal function can be executed, and the sub CPU is in a sleep state in which power consumption is smaller than that in the ON state.
In the first power saving mode,
The CPU is in a sleep state, at least one of the other devices is in a sleep state, and the sub CPU is in an ON state;
In the second power saving mode,
The CPU is in a sleep state, at least one of the other devices is in a power OFF state, and the sub CPU is in an ON state.
A controller for an image processing apparatus.   A printer, a scanner, a copier, or a multifunction machine on which the controller for an image processing apparatus according to claim 1 is mounted.

Images