JP5114370B2 - Information processing apparatus, information processing method, and program thereof - Google Patents

Description

  The present invention relates to an information processing apparatus, and more particularly to its activation process.

  In recent years, MFPs (multifunction printers) have been required to further reduce power consumption as environmental measures that are becoming increasingly demanding. For this purpose, various technologies are used by various companies. Among them, STR (Suspend To RAM) is one of the most effective technologies. This saves the current memory and CPU register state in the main memory, stops power supply to most devices including the CPU and HDD, and writes back the saved memory and register state contents when returning. Thus, it is possible to return at high speed with low power consumption without restarting the OS or the like.

  In such energy saving control by STR, there is a problem that a device whose power is turned off in the energy saving mode can be used without any problem after returning from the energy saving mode. For example, in Patent Document 1, a power hook function that calls a callback function provided in each device driver is registered in the power hook queue for each energy saving control mode at the time of initialization of each device driver. The above problem is overcome by calling the power hook function registered in the power hook queue at the time of shifting to the mode and returning from the energy saving mode, and appropriately performing the process of eliminating the mismatch.

  By the way, the STR mechanism differs depending on the platform, and in a platform adopting an Intel (registered trademark) CPU called x86 series, the contents of the registers such as the CPU and the chipset are saved and restored at the time of switching to and returning to the STR mode. An important operation is handled by a module called BIOS (Basic Input / Output System).

  In addition to these functions, the BIOS has basic functions such as memory setting at startup, various device initialization, OS boot loader deployment and activation. As described above, the BIOS has many functions related to hardware, and among them, the memory operating frequency and FSB (front side bus) are set.

JP 2007-306143 A

  However, some of the registers from which these settings are made are actually determined by the input of signals determined by a combination of hardware such as resistors called straps that are selectively tied to a predetermined logic level. is there. The stage in which the CPU determines these operating frequencies by the BIOS is two stages at the time of start-up and at the time of STR return. At these stages, the signal is in an abnormal state due to noise, hardware failure (failure), or the like. As a result, there is a possibility that an incorrect operating frequency is set and it cannot be started correctly, or it cannot be restored normally by returning from the STR even if it is started.

  Once the memory operating frequency has been determined, the setting once made is not canceled unless the power is turned on / off or the transition to STR mode is made, and the BIOS is forcibly set to the correct value in the BIOS. Even if reset means such as PCI reset is used, the correct memory operating frequency is not obtained. For this reason, in such a state, there is usually no recovery method other than turning the power on and off, resulting in a great disadvantage for the user.

  The present invention has been made in view of the above, and information processing in which a module called BIOS is responsible for important operations such as saving and restoring the contents of registers of the CPU, chipset, etc. when shifting to and returning to the STR mode. In the device, it is possible to avoid a fatal phenomenon as an information processing device that cannot be correctly started or cannot be normally restored by returning from the STR even if the device is started. It aims to be able to avoid the restart with accompanying.

  In order to solve the above-described problems and achieve the object, an information processing apparatus according to the present invention shifts to a low power consumption state in which at least a predetermined register related to designation of a memory operating frequency is cleared, and its low power consumption. Energy saving mode transition / return means for controlling return from the state, memory operating frequency determining means for determining the operating frequency of the memory, and setting the predetermined register according to the determined operating frequency, and low power consumption state A return time setting means for setting the return time of the memory to the timer, and whether or not the contents of the predetermined register are appropriate values before the memory operation is started at the memory operating frequency determined by the memory operating frequency determining means. An information processing apparatus comprising: a register checking means for checking whether the register contents are an inappropriate value. Is the case were, after returning the elapsed after the power saving mode transition-returning means has been the return time set in the timer by the return time setting means and to confirm again register contents.

  Further, the information processing method according to the present invention is an energy-saving method in which the control unit controls the transition to the low power consumption state in which at least a predetermined register related to the designation of the memory operating frequency is cleared and the return from the low power consumption state. The mode shift / return step, the memory operating frequency is determined by the control means, the memory operating frequency determining step for setting the predetermined register according to the determined operating frequency, and the control means from the low power consumption state. A return time setting step for setting the return time of the timer in the timer, and before the memory operation is started at the memory operating frequency determined in the memory operating frequency determining step by the control means, the content of the predetermined register is an appropriate value. A register check step for checking whether or not the register check step is performed, wherein the register check step includes: If it is determined that the content is an inappropriate value, after the return time set in the timer by the return time setting step has elapsed, the register contents are checked again after returning from the energy saving mode transition / return step. Including the step of:

  According to the present invention, the information processing apparatus can avoid a fatal phenomenon as the information processing apparatus that cannot be correctly started or cannot be normally recovered by returning from the low power consumption state even if the information processing apparatus is started. However, there is an effect that a restart with manual power on / off can be avoided.

  Exemplary embodiments of an information processing apparatus according to the present invention will be explained below in detail with reference to the accompanying drawings.

[First Embodiment]
(Configuration of information processing device)
First, the configuration of the information processing apparatus according to the first embodiment of the present invention will be described with reference to FIGS. 1 and 2.

  FIG. 1 is a diagram illustrating an appearance and a schematic configuration of an image forming apparatus as an information processing apparatus according to the first embodiment of the present invention. FIG. 2 is a block diagram illustrating a hardware configuration of a controller board and an engine board provided in the information processing apparatus.

  As illustrated in FIG. 1, the information processing apparatus 100 according to the present exemplary embodiment when implemented as an image forming apparatus includes an operation unit 101 that is a user interface, a main body unit 102, and a paper feeding unit that feeds the main body unit 102. 103 and a paper discharge unit 104 that discharges paper on which an image is formed in the main body unit 102.

  The main body 102 is mounted with a controller board 10 and an engine board 20 as control boards, and a main power supply 30 that supplies power to the entire apparatus. The engine board 20 is a control board for controlling a printer engine and a scanner engine (both not shown) provided in the main body unit 102 and acquiring image data from the scanner engine. In the present embodiment, the controller board 10 serves as a control board for controlling the image forming process and a startup process described later.

  As described above, the information processing apparatus 100 includes the controller board 10 and the engine board 20 as control boards. The controller board 10 is important in this embodiment. The engine board 20 is optional and not essential. That is, the information processing apparatus 100 can also be implemented as an information processing apparatus represented by a PC (personal computer) that includes only the controller board 10. In the present embodiment, it is assumed that the controller board 10 is a system having an STR function and having an Intel x86 architecture CPU, its chipset, and BIOS.

  On such a controller board 10, as a general configuration, a CPU 202 that controls each device via the following ASICs, an ASIC1 203 incorporating a memory controller, a memory (MEM) 204, an ASIC1 203, There is an ASIC3 205 that mediates the engine control unit 207 on the engine board 20 side, and an HDD 206 that stores data sent mainly from the engine control unit 207 side via the ASIC3 205.

  Further, the ASIC2 209 is a device that mediates between the ASIC1 203 and the ASIC4 212, and a ROM1 214 storing the BIOS is connected to the ASIC2 209 via a bus. In addition to this, the ASIC2 209 is connected to the USB interface 211, the RTC (Real Time Clock) 213, and the LED1 210 that displays the state of the board.

  The ASIC 4 212 is connected to an NVRAM 215 that stores various setting information, an operation panel 216 serving as a user input interface, a program storage ROM 2 218, an SD card interface 219, and a network interface 220. The operation panel 216 is connected to an LED 2 217 that indicates various states.

  On the other hand, the engine board 20 includes an engine control unit 207 that processes image data for image formation, and a FAX control unit 208 that controls a FAX engine.

  Next, FIG. 3 shows a functional block diagram of the controller board 10 in the present embodiment, which will be described.

  The energy saving mode transition / restoration unit 301 shown in the same figure shifts to a low power consumption state (hereinafter referred to as STR mode) in which the power of some devices is turned off by the STR function described above, and from the low power consumption state. Control reversion. In this STR mode, the CLKCFG register, which is one of registers related to the designation of the memory operating frequency, is cleared when the power supply to the device is cut off.

  The memory operating frequency determining unit 302 is a means for determining the operating frequency of the MEM 204, determines the operating frequency based on a predetermined input signal (strap), and sets a register related to the designation of the memory operating frequency.

  The return time setting unit 303 is means for setting the return time from the STR mode in the timer, and sets the RTC 213 as a timer so that the return from the STR mode can be performed after the return time has elapsed (specifically, the alarm of the RTC 213) Set the register).

  The register confirmation unit 304 confirms whether or not the contents of the CLKCFG register, which is one of the registers related to the designation of the memory operating frequency, are expected (is an appropriate value) (described later).

  The timer value holding unit 305 is means for holding the current timer setting value (RTC value), and stores the RTC value in the nonvolatile NVRAM 215.

  The return time cancellation unit 306 is means for canceling the return time set in the RTC 213 as a timer by the return time setting unit 303. Specifically, the return time set in the timer is canceled by reflecting the RTC value held by the timer value holding unit 305 in the alarm register of the RTC 213 after STR return.

  Note that the control functions by the above-described units are based on the CPU 202 that controls the entire apparatus and the ASICs that cooperate with the CPU 202 (control unit 300), and each unit from the energy saving mode transition / return unit 301 to the return time release unit 306. The control unit 300 having the CPU 202 as a main body executes the control as a pre-process of the normal startup process in the boot process by the BIOS before the memory operating frequency is determined.

(Operation of the information processing apparatus 100)
Next, the operation of the information processing apparatus 100 according to the present embodiment will be described with reference to FIG.
FIG. 4 is a flowchart for explaining the operation of the information processing apparatus 100 according to the present embodiment.

  In this embodiment, the retry is repeated until the apparatus can be normally started. The program code for performing the following processing is included in the BIOS stored in the ROM 214, and is executed by the CPU 202 as a pre-process of the normal startup process before the memory operation is started at the determined memory operating frequency. Is done.

  First, a startup process associated with power-on or STR return is started (step S401).

  Next, it is confirmed whether the value of the predetermined register is a predetermined expected value (step S402). Here, it is expected that bits 0, 1, and 2 of the CLKCFG register in the ASIC1 203 based on the Intel architecture are 0 (appropriate value).

  At this time, if the value of the CLKCFG register matches the appropriate value, it is further confirmed whether or not the setting value of the RTC 213 (RTC value; specifically, the value of the alarm register of the RTC 213) has been saved (step S403). .

If it is confirmed in step S403 that the RTC value is stored, a process of writing the setting value of the RTC 213 back to the stored RTC value is performed. By this process, the set return time when the timer is set in the following step S406 is canceled (step S404).
On the other hand, if the RTC value is not stored, normal startup processing is performed as it is (step S405).

  If it is confirmed in step S402 that the value of the CLKCFG register is not an appropriate value (that is, if any of bits 0, 1, and 2 of the CLKCFG register is 1), the current setting value (RTC value) of the RTC 213 Is stored (step S406). The current RTC value (that is, the value of the alarm register of the RTC 213) is saved in the next step S407 by using the alarm function of the RTC 213 to generate an alarm two seconds after the current time. Since the contents are changed, the timer may operate at an unexpected location such as when an alarm is set on the OS, and it may not be possible to interrupt or return from Sleep Mode. The RTC value is temporarily stored here so that it can be returned.

Next, a timer is set so that the alarm function of the RTC 213 can return from the STR mode after 2 seconds from the current time (step S407).
And it transfers to STR mode (step S408).
Thereafter, after 2 seconds, the process returns from the STR mode (step S401), and the process after the process of checking the CLKCFG register (step S402) is resumed.
The above is the operation at the time of booting the controller board 10 of the information processing apparatus 100 of the second embodiment.

  By the way, the power supply to the device including the register related to the designation of the memory operating frequency is not interrupted except when the power is turned off and the mode is shifted to the STR mode. For this reason, when an improper setting of this register occurs, the improper setting is retained, causing a malfunction. In the present embodiment, the state of the register is cleared by stopping the power supply to the device by shifting to the STR mode using the STR function. And since normal startup processing is executed after the proper setting is reached, fatal malfunctions such as inability to start can be avoided, and manual power on / off restart is also avoided for the user. can do.

[Second Embodiment]
Next, a second embodiment of the present invention will be described with reference to FIGS.
FIG. 5 is a functional block diagram of the controller board 10 in the second embodiment. FIG. 6 is a flowchart for explaining the operation of the information processing apparatus according to the second embodiment.
In the present embodiment, the hardware configuration is the same as that of the first embodiment described above, and a description thereof will be omitted.

  As shown in FIG. 5, the difference between the present embodiment and the first embodiment is that the control unit 300 further includes a failure information notification unit 501. About others, it is the same as that of 1st Embodiment, and description of another functional block is abbreviate | omitted. In addition, the same code | symbol is attached | subjected to the part which is common in FIG.

The failure information notifying unit 501 which is a feature of the present embodiment indicates that the user has failed if the appropriate value cannot be detected even after the register checking unit 304 repeatedly confirms the contents of the CLKCFG register a certain number of times. While notifying via the LED 2 217 or the operation panel 216, the failure information is stored as a log in the nonvolatile NVRAM 215, and the log is notified to the user at the next startup.
The failure information notification unit 501 performs the following determination in step S605 and processing in step S610.

(Operation of the information processing apparatus 100)
Next, the operation of the information processing apparatus 100 according to this embodiment will be described with reference to FIG.
In the present embodiment, if the failure information notifying unit 501 does not succeed even after a certain number of retries (cannot shift to normal activation processing) or there is failure information at the previous activation, the device is not activated. The feature is that the LED 2 217 as a display means displays a failure to the user.

  First, start-up processing from power-on or STR return is started (step S601).

  Next, it is confirmed whether or not the value of the predetermined register is a predetermined expected value (step S602). Here, it is expected that bits 0, 1, and 2 of the CLKCFG register in the ASIC1 203 based on the Intel architecture are 0 (appropriate value).

  At this time, if the value of the CLKCFG register coincides with an appropriate value, it is further confirmed whether the value of the set value of the RTC 213 (RTC value; specifically, the value of the alarm register of the RTC 213) has been saved (step S603).

If it is confirmed in step S603 that the RTC value is stored, a process of writing the setting value of the RTC 213 back to the stored RTC value is performed (step S604).
On the other hand, if the RTC value is not stored, normal startup processing is performed as it is (step S609).

  If it is confirmed in step S602 that the value of the CLKCFG register is not an appropriate value (when one of bits 0, 1, and 2 of the CLKCFG register is 1), has it been retried for a certain number of times? Alternatively, it is further confirmed whether there is failure information at the time of the previous activation (step S605).

If either of these conditions is met, the LED 2 217 or the operation panel 216 is informed of the failure and notified to the user, and the failure information is saved as a log in the NVRAM 215 of the nonvolatile memory, and a series of startup processes Is finished (step S610).
Further, at the next activation, a failure information log is displayed on the LED 2 217 or the operation panel 216 to notify the user.

  On the other hand, if neither of the conditions in steps S602 and S605 is satisfied, the current setting value (RTC value) of the RTC 213 is stored (step S606). The reason for storing the current RTC value is as described above in the first embodiment.

Thereafter, a timer is set so that the alarm function of the RTC 213 can return from the STR mode after 2 seconds from the current time (step S607).
And it transfers to STR mode (step S608).
Thereafter, the process returns from the STR after 2 seconds (step S601), and the process after the process of confirming the CLKCFG register again (step S602) is resumed.
Heretofore, the second embodiment according to the present invention has been described.

In the present embodiment, when the possibility of failure is detected as described above, the user is notified of the failure and the activation process is terminated. Therefore, usability can be improved.
In the first and second embodiments, the timer set time (return time) for returning from the STR mode by the alarm function of the RTC 213 is set to 2 seconds. However, the present invention is not limited to this. You may change arbitrarily according to the state and performance of the apparatus 100. FIG.

  Note that a program for startup processing executed by the information processing apparatus according to the above-described embodiments is provided by being incorporated in advance in a nonvolatile storage medium such as a ROM as a BIOS program executed by the control unit.

  The above program is recorded in a computer-readable recording medium such as a CD-ROM, a flexible disk (FD), a CD-R, a DVD (Digital Versatile Disk), etc. in an installable or executable format file. It may be configured to be provided.

  Further, the program may be provided by being stored on a computer connected to a network such as the Internet and downloaded via the network. The program may be provided or distributed via a network such as the Internet.

1 is a diagram illustrating an appearance and a schematic configuration of an image forming apparatus as an information processing apparatus according to a first embodiment of the present invention. It is a block diagram which shows the hardware constitutions of the controller board and engine board with which the apparatus is equipped. It is a functional block diagram of the controller board. It is a flowchart for demonstrating operation | movement of the information processing apparatus of 1st Embodiment. It is a functional block diagram of the controller board with which the information processing apparatus of the 2nd Embodiment of this invention is provided. It is a flowchart for demonstrating operation | movement of the information processing apparatus of 2nd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Controller board 20 ... Engine board 30 ... Main power supply part 100 ... Information processing apparatus (image forming apparatus)
DESCRIPTION OF SYMBOLS 101 ... Operation part 102 ... Main-body part 103 ... Paper feed part 104 ... Paper discharge part 301 ... Energy-saving mode transfer / restoration part 302 ... Memory operation frequency determination part 303 ... Return time setting part 304 ... Register confirmation part 305 ... Timer value holding part 306 ... Return time cancellation unit 501 ... Failure information notification unit

Claims (13)

Energy saving mode transition / return means for controlling transition to a low power consumption state in which a predetermined register related to designation of at least a memory operating frequency is cleared and return from the low power consumption state;
A memory operating frequency determining means for determining an operating frequency of the memory and setting the predetermined register in accordance with the determined operating frequency;
A recovery time setting means for setting a recovery time from a low power consumption state in a timer;
An information processing apparatus comprising: register checking means for checking whether or not the content of the predetermined register is an appropriate value before starting the operation of the memory at the memory operating frequency determined by the memory operating frequency determining means Because
When it is determined that the contents of the register are an inappropriate value, the register confirmation unit uses the energy saving mode transition / return unit after the return time set in the timer by the return time setting unit has elapsed. An information processing apparatus that checks the register contents again after returning.   If an inappropriate value is detected again by the register checking means after returning from the low power consumption state, the energy saving mode transition / return means returns to the low power consumption state until an appropriate value can be detected. The information processing apparatus according to claim 1, wherein the transition and the return from the low power consumption state are repeated. A return time releasing means for releasing the setting of the return time to the timer by the return time setting means;
3. The information processing apparatus according to claim 1, wherein when the appropriate value can be detected by the register checking unit, the setting of the return time is canceled by the return time canceling unit.   The information processing apparatus according to any one of claims 1 to 3, wherein an RTC (Real Time Clock) is used as a timer set by the return time setting means.   The information processing apparatus according to any one of claims 1 to 4, wherein the energy saving mode transition / return means is based on a STR (Suspend To RAM) technology. Timer value holding means for holding a set value of the timer,
4. The information processing apparatus according to claim 3, wherein when an inappropriate value is detected by the register checking means, the timer value holding means holds the current set value of the timer.   When the set value of the timer is held by the timer value holding means, the return time release means reflects the held set value of the timer as a current set value on the timer, The information processing apparatus according to claim 6, wherein the setting of the return time to the timer is canceled.   2. The failure information notifying means for notifying the user that a failure has occurred when the register confirmation means cannot detect the appropriate value even after being repeated a certain number of times. Information processing device.   The information processing apparatus according to claim 8, wherein the failure information notification unit notifies failure information via an LED.   The information processing apparatus according to claim 8, wherein the failure information notification unit notifies failure information via an operation panel.   9. The information processing apparatus according to claim 8, wherein the failure information notification unit stores failure information in a nonvolatile memory as a log, and notifies the user of the log at the next startup. Energy saving mode transition / recovery step for controlling transition to a low power consumption state in which at least a predetermined register related to designation of the memory operating frequency is cleared by the control means, and return from the low power consumption state,
A memory operating frequency determining step for determining an operating frequency of the memory by the control means and setting the predetermined register in accordance with the determined operating frequency;
A return time setting step for setting a return time from the low power consumption state in the timer by the control means;
A register checking step for checking whether or not the content of the predetermined register is an appropriate value before starting the operation of the memory at the memory operating frequency determined in the memory operating frequency determining step by the control means. An information processing method,
In the register checking step, when it is determined that the contents of the register are inappropriate values, the energy saving mode transition / return step is performed after the return time set in the timer by the return time setting step has elapsed. An information processing method comprising a step of reconfirming register contents after returning.   A program for causing a computer to execute the information processing method according to claim 12.

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